20 ns 512 kb DRAM with 83 MHz page operation.

Nicky C.C. Lu*, Hu Chao, Wei Hwang, Walter Henkels, T. Rajeevakumar, Hussein Hanafi, Lewis Terman, Robert Franch

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations

Abstract

The authors describe a 128K × 4 DRAM (dynamic random-access memory) designed for high speed while retaining the traditional density advantage of the one-transistor DRAM cell. Waveforms show a row access of 20 ns, measured at 5.0 V, 25°C, and 50 pF load, and column access of 7.5 ns under the same conditions. The high-speed page mode with 12-ns cycle into 60 pF is shown. The resulting data rate is 330 MHz with a page depth of 256 b. The chip is 78 mm2 and was fabricated in a single-poly, double-metal n-well epitaxial CMOS process with an average feature size of 1.3 μm.

Original languageEnglish
Pages (from-to)240-241, 385
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume31
DOIs
StatePublished - 1 Dec 1988

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