20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

Jakub Kedzierski, Peiqi Xuan, Vivek Subramanian, Jeffrey Bokor, Tsu Jae King, Chen-Ming Hu, Erik Anderson

Research output: Contribution to journalArticle

27 Scopus citations


Ast the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μA μm-1 on-current on/off current ratios of 106, for a conservative oxide thickness of 40 angstrom |Vg - Vt| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in |Vt| is obtained in devices with gate lengths ranging from 100 to 20 nm.

Original languageEnglish
Pages (from-to)445-452
Number of pages8
JournalSuperlattices and Microstructures
Issue number5-6
StatePublished - 1 Jan 2000

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    Kedzierski, J., Xuan, P., Subramanian, V., Bokor, J., King, T. J., Hu, C-M., & Anderson, E. (2000). 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain. Superlattices and Microstructures, 28(5-6), 445-452. https://doi.org/10.1006/spmi.2000.0947