2-level FIFO architecture design for switch fabrics in network-on-chip

Po-Tsang Huang*, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures without increasing the buffer sizes. The concept of the shared memory mechanism and multiple accesses for the buffers are developed. The FIFO architecture is implemented and simulated with TSMC 0.13um CMOS technology by HSPICE and Verilog. The operation frequency of the 2-level FIFO reaches 400MHz.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages4863-4866
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period21/05/0624/05/06

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