16nm functional 0.039μm2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate

Hou Yu Chen; Chun Chi Chen; Fu Kuo Hsueh; Jan Tsai Liu; Chih Yen Shen; Chiung Chih Hsu; Shyi Long Shy; Bih Tiao Lin; Hsi Ta Chuang; Cheng San Wu; Chen-Ming Hu; Chien Chao Huang; Fu Liang Yang

doi:10.1109/IEDM.2009.5424252

16nm functional 0.039μm² 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate

Hou Yu Chen^*, Chun Chi Chen, Fu Kuo Hsueh, Jan Tsai Liu, Chih Yen Shen, Chiung Chih Hsu, Shyi Long Shy, Bih Tiao Lin, Hsi Ta Chuang, Cheng San Wu, Chen-Ming Hu, Chien Chao Huang, Fu Liang Yang

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Record area size of 0.039μm² for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic V_dd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

Original language	English
Title of host publication	2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
DOIs	https://doi.org/10.1109/IEDM.2009.5424252
State	Published - 1 Dec 2009
Event	2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States Duration: 7 Dec 2009 → 9 Dec 2009

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2009 International Electron Devices Meeting, IEDM 2009
Country	United States
City	Baltimore, MD
Period	7/12/09 → 9/12/09

Access to Document

10.1109/IEDM.2009.5424252

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Chen, H. Y., Chen, C. C., Hsueh, F. K., Liu, J. T., Shen, C. Y., Hsu, C. C., Shy, S. L., Lin, B. T., Chuang, H. T., Wu, C. S., Hu, C-M., Huang, C. C., & Yang, F. L. (2009). 16nm functional 0.039μm² 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest [5424252] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2009.5424252

Chen, Hou Yu ; Chen, Chun Chi ; Hsueh, Fu Kuo ; Liu, Jan Tsai ; Shen, Chih Yen ; Hsu, Chiung Chih ; Shy, Shyi Long ; Lin, Bih Tiao ; Chuang, Hsi Ta ; Wu, Cheng San ; Hu, Chen-Ming ; Huang, Chien Chao ; Yang, Fu Liang. / 16nm functional 0.039μm² 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate. 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. (Technical Digest - International Electron Devices Meeting, IEDM).

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title = "16nm functional 0.039μm2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate",

abstract = "Record area size of 0.039μm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.",

author = "Chen, {Hou Yu} and Chen, {Chun Chi} and Hsueh, {Fu Kuo} and Liu, {Jan Tsai} and Shen, {Chih Yen} and Hsu, {Chiung Chih} and Shy, {Shyi Long} and Lin, {Bih Tiao} and Chuang, {Hsi Ta} and Wu, {Cheng San} and Chen-Ming Hu and Huang, {Chien Chao} and Yang, {Fu Liang}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/IEDM.2009.5424252",

language = "English",

isbn = "9781424456406",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

booktitle = "2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest",

note = "null ; Conference date: 07-12-2009 Through 09-12-2009",

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Chen, HY, Chen, CC, Hsueh, FK, Liu, JT, Shen, CY, Hsu, CC, Shy, SL, Lin, BT, Chuang, HT, Wu, CS, Hu, C-M, Huang, CC & Yang, FL 2009, 16nm functional 0.039μm² 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424252, Technical Digest - International Electron Devices Meeting, IEDM, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 7/12/09. https://doi.org/10.1109/IEDM.2009.5424252

16nm functional 0.039μm² 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate. / Chen, Hou Yu; Chen, Chun Chi; Hsueh, Fu Kuo; Liu, Jan Tsai; Shen, Chih Yen; Hsu, Chiung Chih; Shy, Shyi Long; Lin, Bih Tiao; Chuang, Hsi Ta; Wu, Cheng San; Hu, Chen-Ming; Huang, Chien Chao; Yang, Fu Liang.

2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. 5424252 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Chen, Hou Yu

AU - Chen, Chun Chi

AU - Hsueh, Fu Kuo

AU - Liu, Jan Tsai

AU - Shen, Chih Yen

AU - Hsu, Chiung Chih

AU - Shy, Shyi Long

AU - Lin, Bih Tiao

AU - Chuang, Hsi Ta

AU - Wu, Cheng San

AU - Hu, Chen-Ming

AU - Huang, Chien Chao

AU - Yang, Fu Liang

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Record area size of 0.039μm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

AB - Record area size of 0.039μm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

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M3 - Conference contribution

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SN - 9781424456406

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest

Y2 - 7 December 2009 through 9 December 2009

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