16nm functional 0.039μm2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate

Hou Yu Chen*, Chun Chi Chen, Fu Kuo Hsueh, Jan Tsai Liu, Chih Yen Shen, Chiung Chih Hsu, Shyi Long Shy, Bih Tiao Lin, Hsi Ta Chuang, Cheng San Wu, Chen-Ming Hu, Chien Chao Huang, Fu Liang Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Record area size of 0.039μm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

Original languageEnglish
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
DOIs
StatePublished - 1 Dec 2009
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: 7 Dec 20099 Dec 2009

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2009 International Electron Devices Meeting, IEDM 2009
CountryUnited States
CityBaltimore, MD
Period7/12/099/12/09

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