160 GHz parametric passive frequency doubler in CMOS 180nm technology

Beng Meng Chen, Zuo-Min Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A parametric CMOS passive frequency doubler is reported in this paper. The circuit is implemented in 180 nm CMOS but oses a conservative 0.5um gate length and produces an output between 150GHz and 162 GHz with a minimum measured conversion loss of 19.15 dB. The maximum output power is -26.9 dBm by -4.25dBm input power. The proposed design series a transmission line at the transistor source and series a 500 Ohms resistance at the transistor body in order to improve the performance.

Original languageEnglish
Title of host publication2015 International Workshop on Electromagnetics
Subtitle of host publicationApplications and Student Innovation Competition, iWEM 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467369527
DOIs
StatePublished - 23 Dec 2015
EventInternational Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015 - Hsin-Chu, Taiwan
Duration: 16 Nov 201518 Nov 2015

Publication series

Name2015 International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015

Conference

ConferenceInternational Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015
CountryTaiwan
CityHsin-Chu
Period16/11/1518/11/15

Keywords

  • CMOS
  • frequency doubler
  • millimeter-wave
  • parametric circuit

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  • Cite this

    Chen, B. M., & Tsai , Z-M. (2015). 160 GHz parametric passive frequency doubler in CMOS 180nm technology. In 2015 International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015 [7365065] (2015 International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/iWEM.2015.7365065