16-nm multigate and multifin MOSFET device and SRAM circuits

Hui Wen Cheng*, Yiming Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (H fin)/fin width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation results are experimentally validated. The multi-fin FinFET (AR = 2) has better channel controllability than the multifin trigate (AR = 1) and multi-fin quasi-planar (AR = 0.5) FETs. A six-transistor (6T) static random access memory (SRAM) using multi-fin FinFETs also provides the largest static noise margin because it supports the highest transconductance in FinFETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multi-fin transistors are further examined, and compared with those of an inverter with single-fin transistors. The multi-fin inverter has a shorter delay because it is dominated by the driving current of the transistor. With respect to random-dopant-induced fluctuations, the multifin FinFET suppresses not only the surface potential but also its variation because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants on the circuits are attenuated. The results of this study provide insight into the DC, and circuit characteristics of multifin transistors and associated random dopant fluctuations.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages32-35
Number of pages4
DOIs
StatePublished - 2010
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 18 Nov 201019 Nov 2010

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Conference

Conference2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period18/11/1019/11/10

Keywords

  • Aspect ratio
  • Coupled device-circuit simulation
  • Delay time
  • Multifin FinFET
  • Random-dopant-position-induced fluctuation
  • Static noise margin

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    Cheng, H. W., & Li, Y. (2010). 16-nm multigate and multifin MOSFET device and SRAM circuits. In 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program (pp. 32-35). [5669144] (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). https://doi.org/10.1109/ISNE.2010.5669144