A new cyclic Analog-to-Digital conversion algorithm with embedded digital error correction is proposed to reduce the linearity errors caused by the comparator inaccuracy and the offset of the S/H operations. New low-voltage fully-balanced current-mode circuits performing the sample/hold, signal-amplification, and current comparison functions are developed to realize a low-voltage current-mode cyclic Analog-to-Digital converter (ADC). With 1.5 V supply voltage and 0.8 μm CMOS device parameters, the HSPICE simulation results show that the designed ADC can achieve 12-bit resolution at 10k/s conversion rate with the power dissipation of the analog circuits less than 2 mW.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1995|
|Event||Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA|
Duration: 30 Apr 1995 → 3 May 1995