1.5 V CMOS current-mode cyclic analog-to-digital converter with digital error correction

Chih Cheng Chen*, Chung-Yu Wu, Jyh Jer Cho

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

A new cyclic Analog-to-Digital conversion algorithm with embedded digital error correction is proposed to reduce the linearity errors caused by the comparator inaccuracy and the offset of the S/H operations. New low-voltage fully-balanced current-mode circuits performing the sample/hold, signal-amplification, and current comparison functions are developed to realize a low-voltage current-mode cyclic Analog-to-Digital converter (ADC). With 1.5 V supply voltage and 0.8 μm CMOS device parameters, the HSPICE simulation results show that the designed ADC can achieve 12-bit resolution at 10k/s conversion rate with the power dissipation of the analog circuits less than 2 mW.

Original languageEnglish
Article number5086540
Pages (from-to)537-540
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

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