A 1.5 V SC filter employing a balanced differential structure and a internal clock booster is proposed. The design technique is demonstrated by a fourth-order bandpass biquad filter fabricated with a standard 0.8 μm CMOS technology. This prototype fourth-order filter which has a center frequency of 8 kHz and a clock frequency of 400 kHz dissipates about 330 μW with a 1.5 V power supply. Including the clock generator and boosters, it occupies 600×1500 μm2. The measurement result shows this filter has the IMD of 0.1 percent for 1.2 VIP differential signal.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1995|
|Event||Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA|
Duration: 30 Apr 1995 → 3 May 1995