1.5 V CMOS balanced differential switched-capacitor filter with internal clock boosters

Chung-Yu Wu*, Wei Shinn Wey, Tasi Chung Yu

*Corresponding author for this work

Research output: Contribution to journalConference article

11 Scopus citations

Abstract

A 1.5 V SC filter employing a balanced differential structure and a internal clock booster is proposed. The design technique is demonstrated by a fourth-order bandpass biquad filter fabricated with a standard 0.8 μm CMOS technology. This prototype fourth-order filter which has a center frequency of 8 kHz and a clock frequency of 400 kHz dissipates about 330 μW with a 1.5 V power supply. Including the clock generator and boosters, it occupies 600×1500 μm2. The measurement result shows this filter has the IMD of 0.1 percent for 1.2 VIP differential signal.

Original languageEnglish
Article number5099956
Pages (from-to)1025-1028
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

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