This paper presents the design and test of a 14 GSps, four-bit data converter pair in 90 nm CMOS suitable for implementing advanced serial links. The data converter pair consists of a noninterleaved flash analog-to-digital converter (ADC) and a noninterleaved current-steering digital-to-analog converter (DAC). Both the converter designs adopt the wave-pipelining technique to increase the available signal settling time. Through detailed analysis, we show that cascading three active feedback preamplifiers to implement the cores of the comparators in the ADC balances the power budget and the design difficulty when we push the sampling rate to the process limit. Current mode logic gates are used to alleviate the power bouncing issue. To address the difficulty and high cost of testing the extremely high-speed converters, the design embeds the simple design-for-testability circuits cooperating with the on-chip resources to provide two cost-effective test modes. The first test mode cascades the ADC and DAC so that they can be tested at the rated speed without the need of a very high speed logic analyzer. The second test mode enables the eye diagram tests by shuffling the digital outputs of ADC as the inputs of the DAC instead of adopting conventional linear feedback shift register. The experimental results show that the cascaded ADC and DAC pair achieves a 31.0 dBc spurious-free dynamic range and a 25.9 dB signal-to-noise-and-distortion ratio with a 1.11 GHz,-1 dBFS stimulus at 14 GSps. The ADC and DAC consume 214 mW and 85 mW from a 1.0-V supply and occupy 0.1575 mm2 and 0.0636 mm 2, respectively.
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - 1 Jan 2014|
- Analog-to-digital converter (ADC)
- digital loopback
- digital-to-analog converter (DAC)
- eye diagram test