135-MHz 258-K gates VLSI design for all-intra H.264/AVC scalable video encoder

Gwo Long Li*, Tzu Yu Chen, Meng Wei Shen, Meng Hsun Wen, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.

Original languageEnglish
Article number6177280
Pages (from-to)636-647
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number4
DOIs
StatePublished - 1 Jan 2013

Keywords

  • All-intra
  • scalable video coding (SVC)
  • VLSI architecture design

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