120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Hsiang An Yang, Chao Chang Chiu, Shin Chi Lai, Jui Lung Chen, Chih Wei Chang, Che Hao Meng, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Chao Cheng Lee, Jian Ru Lin, Tsung Yen Tsai, Hsin Yu Luo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Engineering & Materials Science