120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Hsiang An Yang; Chao Chang Chiu; Shin Chi Lai; Jui Lung Chen; Chih Wei Chang; Che Hao Meng; Ke-Horng Chen; Chin Long Wey; Ying Hsi Lin; Chao Cheng Lee; Jian Ru Lin; Tsung Yen Tsai; Hsin Yu Luo

doi:10.1109/ESSCIRC.2015.7313884

120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Hsiang An Yang, Chao Chang Chiu, Shin Chi Lai, Jui Lung Chen, Chih Wei Chang, Che Hao Meng, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Chao Cheng Lee, Jian Ru Lin, Tsung Yen Tsai, Hsin Yu Luo

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.

Original language	English
Title of host publication	ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
Editors	Franz Dielacher, Wolfgang Pribyl, Gernot Hueber
Publisher	IEEE Computer Society
Pages	291-294
Number of pages	4
ISBN (Electronic)	9781467374705
DOIs	https://doi.org/10.1109/ESSCIRC.2015.7313884
State	Published - 30 Oct 2015
Event	41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria Duration: 14 Sep 2015 → 18 Sep 2015

Publication series

Name	European Solid-State Circuits Conference
Volume	2015-October
ISSN (Print)	1930-8833

Conference

Conference	41st European Solid-State Circuits Conference, ESSCIRC 2015
Country	Austria
City	Graz
Period	14/09/15 → 18/09/15

Keywords

bootstrap operation
high voltage clamping circuit
slew rate enhancement (SRE) technique

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10.1109/ESSCIRC.2015.7313884

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Yang, H. A., Chiu, C. C., Lai, S. C., Chen, J. L., Chang, C. W., Meng, C. H., Chen, K-H., Wey, C. L., Lin, Y. H., Lee, C. C., Lin, J. R., Tsai, T. Y., & Luo, H. Y. (2015). 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. In F. Dielacher, W. Pribyl, & G. Hueber (Eds.), ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference (pp. 291-294). [7313884] (European Solid-State Circuits Conference; Vol. 2015-October). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2015.7313884

Yang, Hsiang An ; Chiu, Chao Chang ; Lai, Shin Chi ; Chen, Jui Lung ; Chang, Chih Wei ; Meng, Che Hao ; Chen, Ke-Horng ; Wey, Chin Long ; Lin, Ying Hsi ; Lee, Chao Cheng ; Lin, Jian Ru ; Tsai, Tsung Yen ; Luo, Hsin Yu. / 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. editor / Franz Dielacher ; Wolfgang Pribyl ; Gernot Hueber. IEEE Computer Society, 2015. pp. 291-294 (European Solid-State Circuits Conference).

@inproceedings{bd3292bf94d44068b1cb0a9ecb51f88e,

title = "120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs",

abstract = "High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.",

keywords = "bootstrap operation, high voltage clamping circuit, slew rate enhancement (SRE) technique",

author = "Yang, {Hsiang An} and Chiu, {Chao Chang} and Lai, {Shin Chi} and Chen, {Jui Lung} and Chang, {Chih Wei} and Meng, {Che Hao} and Ke-Horng Chen and Wey, {Chin Long} and Lin, {Ying Hsi} and Lee, {Chao Cheng} and Lin, {Jian Ru} and Tsai, {Tsung Yen} and Luo, {Hsin Yu}",

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day = "30",

doi = "10.1109/ESSCIRC.2015.7313884",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

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editor = "Franz Dielacher and Wolfgang Pribyl and Gernot Hueber",

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Yang, HA, Chiu, CC, Lai, SC, Chen, JL, Chang, CW, Meng, CH, Chen, K-H, Wey, CL, Lin, YH, Lee, CC, Lin, JR, Tsai, TY & Luo, HY 2015, 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. in F Dielacher, W Pribyl & G Hueber (eds), ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference., 7313884, European Solid-State Circuits Conference, vol. 2015-October, IEEE Computer Society, pp. 291-294, 41st European Solid-State Circuits Conference, ESSCIRC 2015, Graz, Austria, 14/09/15. https://doi.org/10.1109/ESSCIRC.2015.7313884

120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. / Yang, Hsiang An; Chiu, Chao Chang; Lai, Shin Chi; Chen, Jui Lung; Chang, Chih Wei; Meng, Che Hao; Chen, Ke-Horng; Wey, Chin Long; Lin, Ying Hsi; Lee, Chao Cheng; Lin, Jian Ru; Tsai, Tsung Yen; Luo, Hsin Yu.

ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. ed. / Franz Dielacher; Wolfgang Pribyl; Gernot Hueber. IEEE Computer Society, 2015. p. 291-294 7313884 (European Solid-State Circuits Conference; Vol. 2015-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

AU - Yang, Hsiang An

AU - Chiu, Chao Chang

AU - Lai, Shin Chi

AU - Chen, Jui Lung

AU - Chang, Chih Wei

AU - Meng, Che Hao

AU - Chen, Ke-Horng

AU - Wey, Chin Long

AU - Lin, Ying Hsi

AU - Lee, Chao Cheng

AU - Lin, Jian Ru

AU - Tsai, Tsung Yen

AU - Luo, Hsin Yu

PY - 2015/10/30

Y1 - 2015/10/30

N2 - High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.

AB - High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.

KW - bootstrap operation

KW - high voltage clamping circuit

KW - slew rate enhancement (SRE) technique

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DO - 10.1109/ESSCIRC.2015.7313884

M3 - Conference contribution

AN - SCOPUS:84958774626

T3 - European Solid-State Circuits Conference

SP - 291

EP - 294

BT - ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference

A2 - Dielacher, Franz

A2 - Pribyl, Wolfgang

A2 - Hueber, Gernot

PB - IEEE Computer Society

Y2 - 14 September 2015 through 18 September 2015

ER -

Yang HA, Chiu CC, Lai SC, Chen JL, Chang CW, Meng CH et al. 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. In Dielacher F, Pribyl W, Hueber G, editors, ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. IEEE Computer Society. 2015. p. 291-294. 7313884. (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2015.7313884