120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Hsiang An Yang, Chao Chang Chiu, Shin Chi Lai, Jui Lung Chen, Chih Wei Chang, Che Hao Meng, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Chao Cheng Lee, Jian Ru Lin, Tsung Yen Tsai, Hsin Yu Luo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.

Original languageEnglish
Title of host publicationESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
EditorsFranz Dielacher, Wolfgang Pribyl, Gernot Hueber
PublisherIEEE Computer Society
Pages291-294
Number of pages4
ISBN (Electronic)9781467374705
DOIs
StatePublished - 30 Oct 2015
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 14 Sep 201518 Sep 2015

Publication series

NameEuropean Solid-State Circuits Conference
Volume2015-October
ISSN (Print)1930-8833

Conference

Conference41st European Solid-State Circuits Conference, ESSCIRC 2015
CountryAustria
CityGraz
Period14/09/1518/09/15

Keywords

  • bootstrap operation
  • high voltage clamping circuit
  • slew rate enhancement (SRE) technique

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  • Cite this

    Yang, H. A., Chiu, C. C., Lai, S. C., Chen, J. L., Chang, C. W., Meng, C. H., Chen, K-H., Wey, C. L., Lin, Y. H., Lee, C. C., Lin, J. R., Tsai, T. Y., & Luo, H. Y. (2015). 120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. In F. Dielacher, W. Pribyl, & G. Hueber (Eds.), ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference (pp. 291-294). [7313884] (European Solid-State Circuits Conference; Vol. 2015-October). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2015.7313884