A new CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed new combiner circuit, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mVP-P at both inputs. The measured -3 dB bandwidth is 2.2 MHz and the power dissipation is 2.8 mW. The input bandwidth of the multiplier can be designed to reach the GHz range. Simple structure, low-voltage low-power capability, and high performance make the proposed multiplier quite feasible in many applications.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong|
Duration: 9 Jun 1997 → 12 Jun 1997