100MHz pipelined CMOS comparator for flash A/D conversion.

Jieh-Tsorng Wu*, Bruce A. Wooley

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply.

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