10-bit SAR ADC with novel pseudo-random capacitor switching scheme

Pai Hsiang Hsu, Yueh Ru Lee, Chung Chih Hung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
StatePublished - Apr 2019
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 22 Apr 201925 Apr 2019

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period22/04/1925/04/19

Keywords

  • High-performance
  • Low power
  • Pseudo-random
  • Successive-approximation-register analog-to-digital converter

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