1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

Tien Y. Lo*, Chung-Chih Hung

*Corresponding author for this work

Research output: Contribution to journalConference article

5 Scopus citations

Abstract

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

Original languageEnglish
Article number4253507
Pages (from-to)3792-3795
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 27 Sep 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007

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