0.75 V 2.6 GHz digital bang–bang PLL with dynamic double-tail phase detector and supply-noise-tolerant gm-controlled DCO

C. H. Wong*, Y. Li, J. Du, X. Wang, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

A compact low-supply-voltage yet low-noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double-tail latch which enables high time-to-voltage gain and low input-referred noise under tight power-supply headroom. The ring-based digitally controlled oscillator (DCO) is made of multiple gm-controlled delay units and a constant-gm-biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in-band phase noise of −105 dBc/Hz.

Original languageEnglish
Pages (from-to)198-200
Number of pages3
JournalElectronics Letters
Volume54
Issue number4
DOIs
StatePublished - 22 Feb 2018

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