0.5 V DD digitally controlled oscillators design with compensation techniques for PVT variations

Chia Wen Chang*, Shyh-Jye Jou, Yuan Hua Chu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a low voltage and low power digitally controlled oscillator (DCO) with not only wide frequency range and high frequency resolution but also compensation techniques against PVT variations. The frequency range of the 0.5 V DD DCO, implemented in GP-65 nm LVT CMOS process, is from 278 MHz to 25 MHz for portable applications and consumes only 148 μW at 278 MHz and 28.5 μW at 25 MHz. Even in a dirty V DD /GND condition, the peak-to-peak and RMS period jitter are 98.7 and 12.7 ps, respectively. In addition, with compensation techniques used in this work, the effective frequency range is increased by 1.786 times. As a result, compensation techniques in this work are very suitable for the demand of robust design, especially in low-voltage systems or wide PVT environments.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages606-609
Number of pages4
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
Duration: 25 Oct 201128 Oct 2011

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference2011 IEEE 9th International Conference on ASIC, ASICON 2011
CountryChina
CityXiamen
Period25/10/1128/10/11

Keywords

  • All-digital phase-locked loop
  • compensation techniques
  • digitally controlled oscillators
  • low voltage
  • PVT variations

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