0.5-V input digital low-dropout regulator (LDO) with 98.7% current efficiency in 65nm CMOS

Yasuyuki Okuma*, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

Original languageEnglish
Pages (from-to)938-944
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE94-C
Issue number6
DOIs
StatePublished - 1 Jan 2011

Keywords

  • Digital control
  • Low dropout regulator
  • Low voltage

Fingerprint Dive into the research topics of '0.5-V input digital low-dropout regulator (LDO) with 98.7% current efficiency in 65nm CMOS'. Together they form a unique fingerprint.

Cite this