0.5 μm silicon bipolar transistor technology for analog applications

H. Nakajima*, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

A silicon bipolar technology for low power analog applications with a 0.5 μm design rule has been developed. A maximum fT value of 24 GHz ( VCE = 2V, IC = 260 μA) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz ( VCC = 5V, IC = 600 μA).

Original languageEnglish
Pages213-216
Number of pages4
StatePublished - 1994
EventProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: 10 Oct 199411 Oct 1994

Conference

ConferenceProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period10/10/9411/10/94

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