0.5 μm CMOS device design and characterization

H. I. Hanafi; M. R. Wordeman; L. K. Wang; Y. Taur; J. Y.C. Sun; R. H. Dennard; D. S. Zicherman; M. D. Rodriguez; N. Haddad; A. Edenfeld; M. Polavarapu

0.5 μm CMOS device design and characterization

H. I. Hanafi^*, M. R. Wordeman, L. K. Wang, Y. Taur, J. Y.C. Sun, R. H. Dennard, D. S. Zicherman, M. D. Rodriguez, N. Haddad, A. Edenfeld, M. Polavarapu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n⁺polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.

Original language	English
Title of host publication	ESSDERC 1987 - 17th European Solid State Device Research Conference
Publisher	IEEE Computer Society
Pages	91-94
Number of pages	4
ISBN (Electronic)	0444704779
ISBN (Print)	9780444704771
State	Published - 1987
Event	17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy Duration: 14 Sep 1987 → 17 Sep 1987

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	17th European Solid State Device Research Conference, ESSDERC 1987
Country	Italy
City	Bologna
Period	14/09/87 → 17/09/87

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Hanafi, H. I., Wordeman, M. R., Wang, L. K., Taur, Y., Sun, J. Y. C., Dennard, R. H., Zicherman, D. S., Rodriguez, M. D., Haddad, N., Edenfeld, A., & Polavarapu, M. (1987). 0.5 μm CMOS device design and characterization. In ESSDERC 1987 - 17th European Solid State Device Research Conference (pp. 91-94). [5436921] (European Solid-State Device Research Conference). IEEE Computer Society.

Hanafi, H. I. ; Wordeman, M. R. ; Wang, L. K. ; Taur, Y. ; Sun, J. Y.C. ; Dennard, R. H. ; Zicherman, D. S. ; Rodriguez, M. D. ; Haddad, N. ; Edenfeld, A. ; Polavarapu, M. / 0.5 μm CMOS device design and characterization. ESSDERC 1987 - 17th European Solid State Device Research Conference. IEEE Computer Society, 1987. pp. 91-94 (European Solid-State Device Research Conference).

@inproceedings{4dd1c72c744c4efb8729c4ed4c002f05,

title = "0.5 μm CMOS device design and characterization",

abstract = "The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.",

author = "Hanafi, {H. I.} and Wordeman, {M. R.} and Wang, {L. K.} and Y. Taur and Sun, {J. Y.C.} and Dennard, {R. H.} and Zicherman, {D. S.} and Rodriguez, {M. D.} and N. Haddad and A. Edenfeld and M. Polavarapu",

year = "1987",

language = "English",

isbn = "9780444704771",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "91--94",

booktitle = "ESSDERC 1987 - 17th European Solid State Device Research Conference",

address = "United States",

note = "null ; Conference date: 14-09-1987 Through 17-09-1987",

}

Hanafi, HI, Wordeman, MR, Wang, LK, Taur, Y, Sun, JYC, Dennard, RH, Zicherman, DS, Rodriguez, MD, Haddad, N, Edenfeld, A & Polavarapu, M 1987, 0.5 μm CMOS device design and characterization. in ESSDERC 1987 - 17th European Solid State Device Research Conference., 5436921, European Solid-State Device Research Conference, IEEE Computer Society, pp. 91-94, 17th European Solid State Device Research Conference, ESSDERC 1987, Bologna, Italy, 14/09/87.

0.5 μm CMOS device design and characterization. / Hanafi, H. I.; Wordeman, M. R.; Wang, L. K.; Taur, Y.; Sun, J. Y.C.; Dennard, R. H.; Zicherman, D. S.; Rodriguez, M. D.; Haddad, N.; Edenfeld, A.; Polavarapu, M.

ESSDERC 1987 - 17th European Solid State Device Research Conference. IEEE Computer Society, 1987. p. 91-94 5436921 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 0.5 μm CMOS device design and characterization

AU - Hanafi, H. I.

AU - Wordeman, M. R.

AU - Wang, L. K.

AU - Taur, Y.

AU - Sun, J. Y.C.

AU - Dennard, R. H.

AU - Zicherman, D. S.

AU - Rodriguez, M. D.

AU - Haddad, N.

AU - Edenfeld, A.

AU - Polavarapu, M.

PY - 1987

Y1 - 1987

N2 - The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.

AB - The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.

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M3 - Conference contribution

AN - SCOPUS:84907819525

SN - 9780444704771

T3 - European Solid-State Device Research Conference

SP - 91

EP - 94

BT - ESSDERC 1987 - 17th European Solid State Device Research Conference

PB - IEEE Computer Society

Y2 - 14 September 1987 through 17 September 1987

ER -