0.5 μm CMOS device design and characterization

H. I. Hanafi*, M. R. Wordeman, L. K. Wang, Y. Taur, J. Y.C. Sun, R. H. Dennard, D. S. Zicherman, M. D. Rodriguez, N. Haddad, A. Edenfeld, M. Polavarapu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.

Original languageEnglish
Title of host publicationESSDERC 1987 - 17th European Solid State Device Research Conference
PublisherIEEE Computer Society
Pages91-94
Number of pages4
ISBN (Electronic)0444704779
ISBN (Print)9780444704771
StatePublished - 1987
Event17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
Duration: 14 Sep 198717 Sep 1987

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
CountryItaly
CityBologna
Period14/09/8717/09/87

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