0.3 μm BiCMOS technology for mixed analog/digital application systems

H. Nii*, T. Yoshino, K. Inoh, N. Itoh, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata, H. Iwai

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

In this paper, 0.3 μm BiCMOS technology for mixed analog/digital application is presented. This technology includes high fmax and high BVceo NPN transistor, 0.3 μm CMOS, and passive elements. These elements are successfully implemented.

Original languageEnglish
Pages68-71
Number of pages4
StatePublished - 1997
EventProceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: 28 Sep 199730 Sep 1997

Conference

ConferenceProceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period28/09/9730/09/97

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