0.2μm analog CMOS with very low noise figure at 2 GHz operation

T. Ohguro*, E. Morifuji, M. Saito, M. Ono, T. Yoshitomi, H. S. Momose, N. Ito, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations

Abstract

An investigation has been carried out to study the reduction of noise figure of silicon MOSFETs at 2GHz operation. It has been confirmed that reduction in gate length and the resistance of source and drain are effective to reduce the noise. Results suggest a high possibility of deep-submicron CMOS for application into RF front-end telecommunication ICs which have been conventionally produced by using mainly III-V devices.

Original languageEnglish
Pages (from-to)132-133
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 11 Jun 1996
EventProceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 11 Jun 199613 Jun 1996

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