0.15 μm CMOS foundry technology with 0.1 μm devices for high performance applications

C. H. Diaz*, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, Chen-Ming Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. H. Wang, C. C. Wang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

This paper describes a leading-edge 0.15 μm CMOS logic foundry technology family. Advanced core devices using 20 angstroms oxides for 1.2-1.5 V operation (L G_min = 0.1 μm) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 angstroms oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 angstroms gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 μm for M1 and 0.48 μm for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 μm 2 demonstrated in a 2 Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.

Original languageEnglish
Pages (from-to)146-147
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Jan 2000
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 13 Jun 200015 Jun 2000

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