0.12 μm raised gate/source/drain epitaxial channel NMOS technology

T. Ohguro*, H. Naruse, H. Sugaya, H. Kimijima, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalConference article

16 Scopus citations

Abstract

We introduce a 0.12 μm nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 μm nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

Original languageEnglish
Pages (from-to)927-930
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1998
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 6 Dec 19989 Dec 1998

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    Ohguro, T., Naruse, H., Sugaya, H., Kimijima, H., Morifuji, E., Yoshitomi, T., Morimoto, T., Momose, H. S., Katsumata, Y., & Iwai, H. (1998). 0.12 μm raised gate/source/drain epitaxial channel NMOS technology. Technical Digest - International Electron Devices Meeting, 927-930. https://doi.org/10.1109/IEDM.1998.746506