0. 8 mu m Bi-CMOS TECHNOLOGY WITH HIGH F//T ION-IMPLANTED EMITTER BIPOLAR TRANSISTOR.

H. Iwai*, G. Sasaki, Y. Unno, Y. Niitsu, M. Norishima, Y. Sugimoto, K. Kanzaki

*Corresponding author for this work

Research output: Contribution to journalConference article

16 Scopus citations

Abstract

A submicrometer Bi-CMOS (bipolar-CMOS) technology with a direct ion-implanted emitter bipolar transistor was developed using an 0. 8- mu m CMOS process. For the bipolar transistor, an ion-implanted emitter structure was chosen to minimize the production cost. By optimizing the bipolar transistor, a sufficiently high performance for Bi-CMOS gates was obtained. The fabrication-process sequences and resulting device characteristics are described.

Original languageEnglish
Pages (from-to)28-31
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1987

Fingerprint Dive into the research topics of '0. 8 mu m Bi-CMOS TECHNOLOGY WITH HIGH F//T ION-IMPLANTED EMITTER BIPOLAR TRANSISTOR.'. Together they form a unique fingerprint.

  • Cite this