1990 …2022

Research output per year

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Research Output

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Conference contribution
2019

Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Jun 2019, 2019 Silicon Nanoelectronics Workshop, SNW 2019. Institute of Electrical and Electronics Engineers Inc., 8782939. (2019 Silicon Nanoelectronics Workshop, SNW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. & 6 others, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., Apr 2019, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Chang, S. W., Li, J. H., Huang, M. K., Huang, Y. C., Huang, S. T., Wang, H. C., Huang, Y. J., Wang, J. Y., Yu, L. W., Huang, Y. F., Hsueh, F. K., Sung, P. J., Wu, C. T., Ma, W. C. Y., Kao, K. H., Lee, Y. J., Lin, C. L., Chuang, R. W., Huang, K. P., Samukawa, S. & 16 others, Li, Y., Lee, W. H., Chu, T. Y., Chao, T-S., Huang, G. W., Wu, W. F., Li, J. Y., Shieh, J. M., Yeh, W. K., Wang, Y. H., Lu, D. D., Wang, C. J., Lin, N. C., Su, C. J., Lo, S. H. & Huang, H. F., Dec 2019, 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 4 p. 8993525. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. & 16 others, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T-S., Yeh, W. K. & Wang, Y. H., 16 Jan 2019, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations
2018

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment

Yeh, M. S., Luo, G. L., Hou, F. J., Sung, P. J., Wang, C. J., Su, C. J., Wu, C. T., Huang, Y. C., Hong, T. C., Chao, T-S., Chen, B. Y., Chen, K. M., Izawa, M., Miura, M., Morimoto, M., Ishimura, H., Lee, Y. J., Wu, W. F. & Yeh, W. K., 26 Jul 2018, 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 205-207 3 p. 8421457. (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Su, C. J., Hong, T. C., Tsou, Y. C., Hou, F. J., Sung, P. J., Yeh, M. S., Wan, C. C., Kao, K. H., Tang, Y. T., Chiu, C. H., Wang, C. J., Chung, S. T., You, T. Y., Huang, Y. C., Wu, C. T., Lin, K. L., Luo, G. L., Huang, K. P., Lee, Y. J., Chao, T-S. & 5 others, Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 23 Jan 2018, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., p. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations
2017

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Lee, Y. J., Hong, T. C., Hsueh, F. K., Sung, P. J., Chen, C. Y., Chuang, S. S., Cho, T. C., Noda, S., Tsou, Y. C., Kao, K. H., Wu, C. T., Yu, T. Y., Jian, Y. L., Su, C. J., Huang, Y. M., Huang, W. H., Chen, B. Y., Chen, M. C., Huang, K. P., Li, J. Y. & 10 others, Chen, M. J., Li, Y., Samukawa, S., Wu, W. F., Huang, G. W., Shieh, J. M., Tseng, T. Y., Chao, T. S., Wang, Y. H. & Yeh, W. K., 31 Jan 2017, 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 33.5.1-33.5.4 7838535. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K. H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., Hong, T. C. & 10 others, Huang, K. P., Chen, M. C., Lee, Y. J., Chao, T-S., Tseng, T-Y., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 31 Jul 2017, 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., p. T152-T153 7998159. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations
2016

Fabrication and characterization of Pi-gate poly-Si junctionless and inversion mode Fin-FETs for 3-D IC applications

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 27 Sep 2016, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., p. 110-111 2 p. 7578007. (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

Sung, P. J., Cho, T. C., Chen, P. C., Hou, F. J., Lai, C. H., Lee, Y. J., Li, Y., Samukawa, S., Chao, T. S., Wu, W. F. & Yeh, W. K., 21 Nov 2016, 16th International Conference on Nanotechnology - IEEE NANO 2016. Institute of Electrical and Electronics Engineers Inc., p. 174-175 2 p. 7751473. (16th International Conference on Nanotechnology - IEEE NANO 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Investigation of hot carrier reliability of ultrathin poly-Si nanobelt junctionless (UTNB-JL) transistors on different underlying insulators

Chang, J. H., Chung, C. C., Lin, J. Y. & Chao, T-S., 12 Aug 2016, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 7543281. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Low-temperature microwave annealing processes for future IC fabrication

Lee, Y. J., Tsai, B. A., Cho, T. C., Hsueh, F. K., Sung, P. J., Lai, C. H., Luo, C-W. & Chao, T-S., 26 Apr 2016, 2014 IEEE International Nanoelectronics Conference, INEC 2014. Institute of Electrical and Electronics Engineers Inc., 7460453. (2014 IEEE International Nanoelectronics Conference, INEC 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2015

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Lee, Y. J., Hou, F. J., Chuang, S. S., Hsueh, F. K., Kao, K. H., Sung, P. J., Yuan, W. Y., Yao, J. Y., Lu, Y. C., Lin, K. L., Wu, C. T., Chen, H. C., Chen, B. Y., Huang, G. W., Chen, H. J. H., Li, J. Y., Li, Y., Samukawa, S., Chao, T. S., Tseng, T. Y. & 3 others, Wu, W. F., Hou, T. H. & Yeh, W. K., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 15.1.1-15.1.4 7409701. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Lee, Y. J., Cho, T. C., Sung, P. J., Kao, K. H., Hsueh, F. K., Hou, F. J., Chen, P. C., Chen, H. C., Wu, C. T., Hsu, S. H., Chen, Y. J., Huang, Y. M., Hou, Y. F., Huang, W. H., Yang, C. C., Chen, B. Y., Lin, K. L., Chen, M. C., Shen, C. H., Huang, G. W. & 8 others, Huang, K. P., Current, M. I., Li, Y., Samukawa, S., Wu, W. F., Shieh, J. M., Chao, T. S. & Yeh, W. K., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.2.1-6.2.4 7409638. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

Kuo, P. Y., Lin, J. Y. & Chao, T-S., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.3.1-6.3.4 7409639. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Simulations of electric field distributions by the susceptor-coupling effects for 2.45GHz microwave inside microwave chamber

Hsueh, F. K., Chang, C. C., Huang, K. P., Lee, Y. J., Wu, W. F. & Chao, T-S., 25 Aug 2015, Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., p. 385-388 4 p. 7224422. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2012

Microwave annealing

Lee, Y. J., Cho, T. C., Chuang, S. S., Hsueh, F. K., Lu, Y. L., Sung, P. J., Chen, S. J., Lo, C. H., Lai, C. H., Current, M. I., Tseng, T-Y., Chao, T-S. & Yang, F. L., 1 Dec 2012, Ion Implantation Technology 2012 - Proceedings of the 19th International Conference on Ion Implantation Technology. p. 123-128 6 p. (AIP Conference Proceedings; vol. 1496).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

NH 3 plasma treatment for flash memory on poly-Si thin films

Lin, Y. H., You, H. C., Chou, J. C., Chou, T. H. & Chao, T-S., 30 Jul 2012, Proceedings - 2012 International Symposium on Computer, Consumer and Control, IS3C 2012. p. 825-828 4 p. 6228435. (Proceedings - 2012 International Symposium on Computer, Consumer and Control, IS3C 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2011

A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

Tsai, T. I., Chao, T-S., Lin, H-C., Huang, T. Y. & Wei, Y. J., 26 Sep 2011, 4th IEEE International NanoElectronics Conference, INEC 2011. 5991710. (Proceedings - International NanoElectronics Conference, INEC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Formation of inverted-pyramid structure by modifying laser processing parameters and acid etching time

Lin, J. W., Liu, E. T., Wu, C. H., Hsieh, I. J. & Chao, T-S., 1 Dec 2011, Student Posters (General) - 219th ECS Meeting. 31 ed. p. 67-72 6 p. (ECS Transactions; vol. 35, no. 31).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

High performance Cu-doped SiO2 ReRAM by a novel chemical soak method

Chin, F. T., Yang, W. L., Chao, T-S., Chang, Y. M., Lin, L. M., Liu, S. H. & Lin, C. H., 1 Dec 2011, Physics and Technology of High-k Materials 9. 3 ed. p. 469-473 5 p. (ECS Transactions; vol. 41, no. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access
1 Scopus citations

Improvement of polycrystalline silicon thin-film transistors with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation

Wu, S. C., Hou, T-H., Chuang, S. H., Chao, T-S. & Lei, T. F., 1 Dec 2011, 2011 International Semiconductor Device Research Symposium, ISDRS 2011. 6135386. (2011 International Semiconductor Device Research Symposium, ISDRS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low temperature polycrystalline Si nanowire devices with gate-all-around Al 2 O 3 /TiN structure using an implant-free technique

Tsai, T. I., Chao, T-S., Su, C. J., Lin, H. C., Huang, T. Y., Lin, H-C. & Wei, Y. J., 26 Sep 2011, 4th IEEE International NanoElectronics Conference, INEC 2011. 5991733. (Proceedings - International NanoElectronics Conference, INEC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Novel GAA raised source / drain sub-10-nm poly-Si NW channel TFTs with self-aligned corked gate structure for 3-D IC applications

Lu, Y. H., Kuo, P. Y., Wu, Y. H., Chen, Y. H. & Chao, T-S., 16 Sep 2011, 2011 Symposium on VLSI Technology, VLSIT 2011 - Digest of Technical Papers. p. 142-143 2 p. 5984675. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Scopus citations
2010

Fluorinated CMOS HfO2 for high performance (HP) and low stand-by power (LSTP) application by pre- and post-CF4 Plasma Passivation

Wu, W. C., Lai, C. S., Chiu, H. H., Wang, J. C., Chou, P. C. & Chao, T-S., 15 Dec 2010, 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010. p. 416-419 4 p. 5618191. (2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Improvements of Fermi-level pinning and NBTI by fluorinated HfO 2-CMOS

Lai, C. S., Wu, W. C., Chiu, H. H., Wang, J. C., Chou, P. C. & Chao, T-S., 1 Dec 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 5713757. (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Influence of postdeposition annealing on physical and electrical properties of high-k Yb2TiO5 gate dielectrics

Pan, T. M., Yen, L. C., Chiang, C. H. & Chao, T-S., 30 Dec 2010, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment. 1 ed. p. 247-252 6 p. (ECS Transactions; vol. 28, no. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Structural and electrical properties of high-k HoTiO3 gate dielectrics

Pan, T. M., Yen, L. C., Hu, C. W. & Chao, T-S., 30 Dec 2010, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment. 1 ed. p. 241-245 5 p. (ECS Transactions; vol. 28, no. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations
2009

3D 65nm CMOS with 320°C microwave dopant activation

Lee, Y. J., Lu, Y. L., Hsueh, F. K., Huang, K. C., Wan, C. C., Cheng, T. Y., Han, M. H., Kowalski, J. M., Kowalski, J. E., Heh, D., Chuang, H. T., Li, Y., Chao, T. S., Wu, C. Y. & Yang, F. L., 1 Dec 2009, 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 54244263. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Trapping/Detrapping characteristics of electrons and holes under dynamic NBTI stress on Hf0 2 and HfSiON gate dielectrics

Lin, W. L., Lou, J. C., Lee, Y. J. & Chao, T-S., 16 Nov 2009, Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. p. 122-125 4 p. 5232685. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2008

Fluorinated HfO 2 gate dielectrics engineering for CMOS by pre-and post-CF 4 plasma passivation

Wu, W. C., Lai, C. S., Lee, S. C., Ming-Wen, M., Chao, T-S., Wang, J. C., Hsu, C. W., Chou, P. C., Chen, J. H., Kao, K. H., Lo, W. C., Lu, T. Y., Tay, L. L. & Rowell, N., 1 Dec 2008, 2008 IEEE International Electron Devices Meeting, IEDM 2008. 4796706. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

SONOS memories with embedded silicon nanocrystals in nitride by in-situ deposition method

Wu, Y. H., Chiang, T. Y., Liu, S. H., Yang, W. L., Chao, T-S. & Chin, F. T., 22 Sep 2008, Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. p. 195-198 4 p. 4567277. (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Trapping and de-trapping characteristics in PBTI and dynamic PBTI between HfO 2 and HfSiON gate dielectrics

Lin, W. L., Lee, Y. J., Lo, W. C., Chen, K. S., Hou, Y. T., Lin, K. C. & Chao, T-S., 23 Sep 2008, 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 4588199. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations
2007

A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness

Wu, W. C., Chao, T-S., Peng, W. C., Yang, W. L., Wang, J. C., Chen, J. H., Ma, M. W., Lai, C. S., Yang, T. Y., Chen, T. P., Chen, C. H., Lin, C. H., Chen, H. H. & Ko, J., 26 Sep 2007, 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers. 4239464. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gray-level patterning of gold nanoparticles with scanning probe lithography of self-assembly monolayer

Sheu, J-T., Wu, C. H., Liu, H. H. & Chao, T-S., 1 Dec 2007, Digest of Papers - Microprocesses and Nanotechnology 2007; 20th International Microprocesses and Nanotechnology Conference, MNC. p. 458-459 2 p. 4456302. (Digest of Papers - Microprocesses and Nanotechnology 2007; 20th International Microprocesses and Nanotechnology Conference, MNC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Impacts of a buffer layer and Hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layer

Tsai, T. I., Lee, Y. J., Chen, K. S., Wang, J., Wan, C. C., Hsueh, F. K., Lin, H-C., Chao, T-S. & Huang, T. Y., 1 Dec 2007, 2007 International Semiconductor Device Research Symposium, ISDRS. 4422397. (2007 International Semiconductor Device Research Symposium, ISDRS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-κ gate dielectric

Yang, T. Y., Ma, M. W., Kao, K. H., Su, C. J., Chao, T-S. & Lei, T. F., 1 Dec 2007, AD'07 - Proceedings of Asia Display 2007. p. 519-522 4 p. (AD'07 - Proceedings of Asia Display 2007; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mobility improvement of HfO2 LTPS TFTs with nitrogen implantation

Ma, M. W., Yang, T. Y., Kao, K. H., Su, C. J., Chen, C. Y., Chao, T-S. & Lei, T. F., 1 Dec 2007, AD'07 - Proceedings of Asia Display 2007. p. 674-677 4 p. (AD'07 - Proceedings of Asia Display 2007; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance enhancement for strained HfCO2 nMOSFET with Contact Etch Stop Layer (CESL) under pulsed-IV measurement

Wu, W. C., Chao, T-S., Chiu, T. H., Wang, J. C., Lai, C. S., Ming-Wen, M., Lo, W. C. & Ho, Y. H., 1 Dec 2007, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. p. 161-164 4 p. 4450087. (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reliability of strained-channel NMOSFETs with SiN capping layer on Hi-wafers with a thin LPCVD-TEOS buffer layer

Tsai, T. I., Lee, Y. J., Chen, K. S., Wang, J., Wan, C. C., Hsueh, F. K., Lin, H-C., Chao, T-S. & Huang, T. Y., 1 Dec 2007, 2007 International Semiconductor Device Research Symposium, ISDRS. 4422398. (2007 International Semiconductor Device Research Symposium, ISDRS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory

Wang, K. T., Chao, T-S., Wu, W. C. & Lai, C. S., 1 Dec 2007, 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. p. 51-54 4 p. 4547617. (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2006

Impacts of high-κ offset spacer on 65-nm node SOI devices

Ma, M. W., Chao, T-S., Kao, K. H., Huang, J. S. & Lei, T. F., 12 Dec 2006, 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings. p. 697-700 4 p. (2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Local Strained Channel (LSC) nMOSFETs by different poly-Si gate and SiN capping layer thicknesses: Mobility enhancement, size dependence, and hot carrier stress

Lee, Y. J., Fan, C. H., Yang, W. L., Lin, W. Y., Huang, B. R., Chao, T-S. & Chuu, D. S., 1 Dec 2006, Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. p. 88-91 4 p. 4017029. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2005

2-bit Poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate

Lin, Y. H., Chien, C-H., Chou, T. H., Chao, T-S., Chang, C. Y. & Lei, T. F., 1 Dec 2005, IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. p. 927-930 4 p. 1609511. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Preparation of nano-scale patterns on the silicon oxide surface by dip-pen nanolithography

Sheu, J-T., Wu, C. H., Liu, H. H. & Chao, T-S., 1 Dec 2005, 2005 5th IEEE Conference on Nanotechnology. p. 895-898 4 p. 1500862. (2005 5th IEEE Conference on Nanotechnology; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2003

Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH3 and N2O nitridation

Chao, T-S. & Chang, T. H., 1 Jan 2003, VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 255-258 4 p. 1252601. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2002

Process-related reliability issues toward sub-100 nm device regime

Chang, C. Y., Chao, T-S., Lin, H-C. & Chien, C-H., 1 Jan 2002, 2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings. IEEE Computer Society, p. 133-140 8 p. 1003159. (2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2001

An implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation

Li, Y-M., Chen, C. K., Lin, S. S., Chao, T. S., Lin, J. L. & Sze, S. M., 1 Jan 2001, Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001. Institute of Electrical and Electronics Engineers Inc., 925022. (Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

High-frequency characteristics of PMOS transistors with raised SiGe source/drain

Chen, K. M., Huang, H. J., Huang, G. W., Chao, T-S., Pai, Y. H. & Chang, C. Y., 1 Jan 2001, 2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2001. Ponchak, G. E. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 92-95 4 p. 942347. (2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2001).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Parallel dynamic load balancing for semiconductor device simulations on a linux cluster

Li, Y-M., Lin, S. S., Yu, S. M., Liu, J. L., Chao, T. S. & Sze, S. M., 1 Dec 2001, 2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001. Laudon, M. & Romanowicz, B. (eds.). p. 538-541 4 p. (2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations