1990 …2022

Research output per year

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Research Output

2020

Characteristics of Poly-Si Junctionless FinFETs with HfZrO Using Forming Gas Annealing

Chung, S. T., Lee, Y. J. & Chao, T. S., 1 Jan 2020, In : IEEE Transactions on Nanotechnology. 19, p. 390-396 7 p., 9091928.

Research output: Contribution to journalArticle

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Feb 2020, In : IEEE Transactions on Electron Devices. 67, 2, p. 711-716 6 p., 8951114.

Research output: Contribution to journalArticle

2 Scopus citations

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Sung, P. J., Su, C. J., Lo, S. H., Hsueh, F. K., Lu, D. D., Lee, Y. J. & Chao, T. S., 1 Jan 2020, In : IEEE Journal of the Electron Devices Society. 8, p. 474-480 7 p., 9063644.

Research output: Contribution to journalArticle

Open Access

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Sung, P-J., Chang, S-W., Kao, K-H., Wu, C-T., Su, C-J., Cho, T-C., Hsueh, F-K., Lee, W-H., Lee, Y-J. & Chao, T-S., 23 Jul 2020, In : Ieee Transactions On Electron Devices. 67, 9, p. 3504-3509 6 p.

Research output: Contribution to journalArticle

Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs

Shen, C. H., Chen, W. Y., Lee, S. Y., Kuo, P. Y. & Chao, T. S., 1 Jan 2020, In : IEEE Transactions on Nanotechnology. 19, p. 322-327 6 p., 9044627.

Research output: Contribution to journalArticle

2019

Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Jun 2019, 2019 Silicon Nanoelectronics Workshop, SNW 2019. Institute of Electrical and Electronics Engineers Inc., 8782939. (2019 Silicon Nanoelectronics Workshop, SNW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Nov 2019, In : IEEE Electron Device Letters. 40, 11, p. 1708-1711 4 p., 8835096.

Research output: Contribution to journalArticle

4 Scopus citations

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. & 6 others, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., Apr 2019, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Chang, S. W., Li, J. H., Huang, M. K., Huang, Y. C., Huang, S. T., Wang, H. C., Huang, Y. J., Wang, J. Y., Yu, L. W., Huang, Y. F., Hsueh, F. K., Sung, P. J., Wu, C. T., Ma, W. C. Y., Kao, K. H., Lee, Y. J., Lin, C. L., Chuang, R. W., Huang, K. P., Samukawa, S. & 16 others, Li, Y., Lee, W. H., Chu, T. Y., Chao, T-S., Huang, G. W., Wu, W. F., Li, J. Y., Shieh, J. M., Yeh, W. K., Wang, Y. H., Lu, D. D., Wang, C. J., Lin, N. C., Su, C. J., Lo, S. H. & Huang, H. F., Dec 2019, 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 4 p. 8993525. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode TFTs

Hsieh, D. R., Lin, K. C. & Chao, T-S., 1 Jan 2019, In : IEEE Journal of the Electron Devices Society. 7, p. 268-275 8 p., 8630465.

Research output: Contribution to journalArticle

Open Access
1 Scopus citations
Open Access

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. & 16 others, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T-S., Yeh, W. K. & Wang, Y. H., 16 Jan 2019, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations
2018

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment

Yeh, M. S., Luo, G. L., Hou, F. J., Sung, P. J., Wang, C. J., Su, C. J., Wu, C. T., Huang, Y. C., Hong, T. C., Chao, T-S., Chen, B. Y., Chen, K. M., Izawa, M., Miura, M., Morimoto, M., Ishimura, H., Lee, Y. J., Wu, W. F. & Yeh, W. K., 26 Jul 2018, 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 205-207 3 p. 8421457. (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Su, C. J., Hong, T. C., Tsou, Y. C., Hou, F. J., Sung, P. J., Yeh, M. S., Wan, C. C., Kao, K. H., Tang, Y. T., Chiu, C. H., Wang, C. J., Chung, S. T., You, T. Y., Huang, Y. C., Wu, C. T., Lin, K. L., Luo, G. L., Huang, K. P., Lee, Y. J., Chao, T-S. & 5 others, Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 23 Jan 2018, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., p. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs

Hsieh, D. R., Chan, Y. D., Kuo, P. Y. & Chao, T-S., 7 Feb 2018, In : IEEE Journal of the Electron Devices Society. 6, 1, p. 314-319 6 p.

Research output: Contribution to journalArticle

Open Access
2 Scopus citations

Junctionless FETs with a Fin Body for Multi-V TH and Dynamic Threshold Operation

Kumar, M. P. V., Lin, J. Y., Kao, K. H. & Chao, T-S., 1 Aug 2018, In : IEEE Transactions on Electron Devices. 65, 8, p. 3535-3542 8 p., 8399532.

Research output: Contribution to journalArticle

4 Scopus citations

Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

Lin, J. Y., Kumar, M. P. V. & Chao, T-S., 1 Jan 2018, In : IEEE Electron Device Letters. 39, 1, p. 8-11 4 p., 8126800.

Research output: Contribution to journalArticle

10 Scopus citations

Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs with RTA-Improved Crystallinity

Shen, C. H., Kuo, P. Y., Chung, C. C., Lee, S. Y. & Chao, T-S., 1 Apr 2018, In : IEEE Electron Device Letters. 39, 4, p. 512-515 4 p.

Research output: Contribution to journalArticle

4 Scopus citations

Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation with Different Body Doping Concentrations

Lin, J. Y., Tsai, C. Y., Shen, C. H., Chung, C. C., Kumar, M. P. V. & Chao, T-S., 1 Sep 2018, In : IEEE Electron Device Letters. 39, 9, p. 1326-1329 4 p., 8417437.

Research output: Contribution to journalArticle

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chung, C. C. C., Shen, C. H., Lin, J. Y., Chin, C. C. & Chao, T-S., 1 Feb 2018, In : IEEE Transactions on Electron Devices. 65, 2, p. 756-762 7 p., 8233410.

Research output: Contribution to journalArticle

12 Scopus citations
2017

Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 1 Jul 2017, In : IEEE Transactions on Electron Devices. 64, 7, p. 2992-2998 7 p., 7934337.

Research output: Contribution to journalArticle

2 Scopus citations

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Lee, Y. J., Hong, T. C., Hsueh, F. K., Sung, P. J., Chen, C. Y., Chuang, S. S., Cho, T. C., Noda, S., Tsou, Y. C., Kao, K. H., Wu, C. T., Yu, T. Y., Jian, Y. L., Su, C. J., Huang, Y. M., Huang, W. H., Chen, B. Y., Chen, M. C., Huang, K. P., Li, J. Y. & 10 others, Chen, M. J., Li, Y., Samukawa, S., Wu, W. F., Huang, G. W., Shieh, J. M., Tseng, T. Y., Chao, T. S., Wang, Y. H. & Yeh, W. K., 31 Jan 2017, 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 33.5.1-33.5.4 7838535. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

Hsieh, D. R., Kuo, P. Y., Lin, J. Y., Chen, Y. H., Chang, T. S. & Chao, T-S., 9 Jan 2017, In : Semiconductor Science and Technology. 32, 2, 025004.

Research output: Contribution to journalArticle

2 Scopus citations

High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Sung, P. J., Cho, T. C., Hou, F. J., Hsueh, F. K., Chung, S. T., Lee, Y. J., Current, M. I. & Chao, T-S., 1 May 2017, In : IEEE Transactions on Electron Devices. 64, 5, p. 2054-2060 7 p., 7885526.

Research output: Contribution to journalArticle

3 Scopus citations

Improving the Electrical Performance of a Quantum Well FET with a Shell Doping Profile by Heterojunction Optimization

Kumar, M. P. V., Hu, C. Y., Walke, A. M., Kao, K. H. & Chao, T-S., 1 Sep 2017, In : IEEE Transactions on Electron Devices. 64, 9, p. 3563-3568 6 p., 7990547.

Research output: Contribution to journalArticle

3 Scopus citations

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K. H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., Hong, T. C. & 10 others, Huang, K. P., Chen, M. C., Lee, Y. J., Chao, T-S., Tseng, T-Y., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 31 Jul 2017, 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., p. T152-T153 7998159. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations
2016

Fabrication and characterization of Pi-gate poly-Si junctionless and inversion mode Fin-FETs for 3-D IC applications

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 27 Sep 2016, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., p. 110-111 2 p. 7578007. (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 1 Nov 2016, In : IEEE Transactions on Electron Devices. 63, 11, p. 4179-4184 6 p., 7582399.

Research output: Contribution to journalArticle

7 Scopus citations

High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

Sung, P. J., Cho, T. C., Chen, P. C., Hou, F. J., Lai, C. H., Lee, Y. J., Li, Y., Samukawa, S., Chao, T. S., Wu, W. F. & Yeh, W. K., 21 Nov 2016, 16th International Conference on Nanotechnology - IEEE NANO 2016. Institute of Electrical and Electronics Engineers Inc., p. 174-175 2 p. 7751473. (16th International Conference on Nanotechnology - IEEE NANO 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Investigation of hot carrier reliability of ultrathin poly-Si nanobelt junctionless (UTNB-JL) transistors on different underlying insulators

Chang, J. H., Chung, C. C., Lin, J. Y. & Chao, T-S., 12 Aug 2016, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 7543281. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Lin, J. Y., Kuo, P. Y., Lin, K. L., Chin, C. C. & Chao, T-S., 1 Dec 2016, In : IEEE Transactions on Electron Devices. 63, 12, p. 4998-5003 6 p., 7676340.

Research output: Contribution to journalArticle

13 Scopus citations

Label-free and real-time detection of ferritin using a horn-like polycrystalline-silicon nanowire field-effect transistor biosensor

Yen, L. C., Pan, T. M., Lee, C. H. & Chao, T-S., 1 Jul 2016, In : Sensors and Actuators, B: Chemical. 230, p. 398-404 7 p.

Research output: Contribution to journalArticle

17 Scopus citations

Low-temperature microwave annealing processes for future IC fabrication

Lee, Y. J., Tsai, B. A., Cho, T. C., Hsueh, F. K., Sung, P. J., Lai, C. H., Luo, C-W. & Chao, T-S., 26 Apr 2016, 2014 IEEE International Nanoelectronics Conference, INEC 2014. Institute of Electrical and Electronics Engineers Inc., 7460453. (2014 IEEE International Nanoelectronics Conference, INEC 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2015

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

Lee, Y. J., Cho, T. C., Kao, K. H., Sung, P. J., Hsueh, F. K., Huang, P. C., Wu, C. T., Hsu, S. H., Huang, W. H., Chen, H. C., Li, Y., Current, M. I., Hengstebeck, B., Marino, J., Büyüklimanli, T., Shieh, J. M., Chao, T. S., Wu, W. F. & Yeh, W. K., 20 Feb 2015, In : Technical Digest - International Electron Devices Meeting, IEDM. 2015-February, February, p. 32.7.1-32.7.4 7047158.

Research output: Contribution to journalConference article

20 Scopus citations

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Lee, Y. J., Hou, F. J., Chuang, S. S., Hsueh, F. K., Kao, K. H., Sung, P. J., Yuan, W. Y., Yao, J. Y., Lu, Y. C., Lin, K. L., Wu, C. T., Chen, H. C., Chen, B. Y., Huang, G. W., Chen, H. J. H., Li, J. Y., Li, Y., Samukawa, S., Chao, T. S., Tseng, T. Y. & 3 others, Wu, W. F., Hou, T. H. & Yeh, W. K., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 15.1.1-15.1.4 7409701. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Lee, Y. J., Cho, T. C., Sung, P. J., Kao, K. H., Hsueh, F. K., Hou, F. J., Chen, P. C., Chen, H. C., Wu, C. T., Hsu, S. H., Chen, Y. J., Huang, Y. M., Hou, Y. F., Huang, W. H., Yang, C. C., Chen, B. Y., Lin, K. L., Chen, M. C., Shen, C. H., Huang, G. W. & 8 others, Huang, K. P., Current, M. I., Li, Y., Samukawa, S., Wu, W. F., Shieh, J. M., Chao, T. S. & Yeh, W. K., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.2.1-6.2.4 7409638. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application

Chen, Y. H., Ma, W. C. Y. & Chao, T-S., 1 Sep 2015, In : Semiconductor Science and Technology. 30, 10, 105017.

Research output: Contribution to journalArticle

10 Scopus citations

Impact of Crystallization Method on Poly-Si Tunnel FETs

Chen, Y. H., Ma, W. C. Y., Lin, J. Y., Lin, C. Y., Hsu, P. Y., Huang, C. Y. & Chao, T-S., 1 Oct 2015, In : IEEE Electron Device Letters. 36, 10, p. 1060-1062 3 p., 7194770.

Research output: Contribution to journalArticle

9 Scopus citations

Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Kumar, M. P. V., Hu, C. Y., Kao, K. H., Lee, Y. J. & Chao, T-S., 7 Sep 2015, In : IEEE Transactions on Electron Devices. 62, 11, p. 3541-3546 6 p., 7244201.

Research output: Contribution to journalArticle

20 Scopus citations

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

Kuo, P. Y., Lin, J. Y. & Chao, T-S., 16 Feb 2015, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.3.1-6.3.4 7409639. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Simulations of electric field distributions by the susceptor-coupling effects for 2.45GHz microwave inside microwave chamber

Hsueh, F. K., Chang, C. C., Huang, K. P., Lee, Y. J., Wu, W. F. & Chao, T-S., 25 Aug 2015, Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., p. 385-388 4 p. 7224422. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Switching characteristics in Cu:SiO2 by chemical soak methods for resistive random access memory (ReRAM)

Chin, F. T., Lin, Y. H., Yang, W. L., Liao, C. H., Lin, L. M., Hsiao, Y. P. & Chao, T-S., 1 Jan 2015, In : Solid-State Electronics. 103, p. 190-194 5 p.

Research output: Contribution to journalArticle

7 Scopus citations
2014

Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application

Chin, F. T., Lin, Y. H., You, H. C., Yang, W. L., Lin, L. M., Hsiao, Y. P., Ko, C. M. & Chao, T-S., 1 Jan 2014, In : Nanoscale Research Letters. 9, 1

Research output: Contribution to journalArticle

Open Access
9 Scopus citations

Characterization of ultra-thin Ni silicide film by two-step low temperature microwave anneal

Wu, C. T., Lee, Y. J., Hsueh, F. K., Sung, P. J., Cho, T. C., Current, M. I. & Chao, T-S., 1 Jan 2014, In : ECS Journal of Solid State Science and Technology. 3, 5

Research output: Contribution to journalArticle

1 Scopus citations

Effect of sensing film thickness on sensing characteristics of dual-gate poly-si ion-sensitive field-effect-transistors

Yen, L. C., Tang, M. T., Tan, C. Y., Pan, T. M. & Chao, T-S., 1 Dec 2014, In : IEEE Electron Device Letters. 35, 12, p. 1302-1304 3 p., 6954697.

Research output: Contribution to journalArticle

5 Scopus citations

High-performance GAA sidewall-damascened sub-10-nm in situ n+-doped poly-Si NWs channels junctionless FETs

Kuo, P. Y., Lu, Y. H. & Chao, T-S., 1 Nov 2014, In : IEEE Transactions on Electron Devices. 61, 11, p. 3821-3826 6 p., 6897955.

Research output: Contribution to journalArticle

18 Scopus citations

Improvement in pH sensitivity of low-temperature polycrystalline-silicon thin-film transistor sensors using H2 sintering

Yen, L. C., Tang, M. T., Chang, F. Y., Pan, T. M., Chao, T-S. & Lee, C. H., 25 Feb 2014, In : Sensors (Switzerland). 14, 3, p. 3825-3832 8 p.

Research output: Contribution to journalArticle

Open Access
5 Scopus citations

Ion-bombarded and plasma-passivated charge storage layer for SONOS-type nonvolatile memory

Liu, S. H., Wu, C. C., Yang, W. L., Lin, Y. H. & Chao, T-S., 1 Jan 2014, In : IEEE Transactions on Electron Devices. 61, 9, p. 3179-3185 7 p., 6872548.

Research output: Contribution to journalArticle

2 Scopus citations