Projects per year
Personal profile
Research Interests
Physics of Semiconductor Devices, Thin Films Deposition Techniques, ULSI Technology, Deep-Submicron Devices Fabrications, Ultra-thin Oxide Preparations, Ultra-clean Processes
Experience
1992/7-2001/8 Associate Researcher / Researcher, National Nano Device Labs
2001/8-2002/1 Associate Prof., Dept. Of Electrophysics, NCTU
2002/2-present Prof., Dept. Of Electrophysics, NCTU
2009-2011 Chairman, Department of Electrophysics, NCTU, Taiwan
Education/Academic qualification
PhD, National Chiao Tung University
External positions
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Projects
利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
Service Proposal for Precious Instruments of National Chiao-Tung University
1/12/19 → 31/12/20
Project: Government Ministry › Ministry of Science and Technology
利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
Development of High Performance/ Low Power Si/SiGe Devices for 3DIC Applications
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
Research Output
Characteristics of Poly-Si Junctionless FinFETs with HfZrO Using Forming Gas Annealing
Chung, S. T., Lee, Y. J. & Chao, T. S., 1 Jan 2020, In : IEEE Transactions on Nanotechnology. 19, p. 390-396 7 p., 9091928.Research output: Contribution to journal › Article
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Feb 2020, In : IEEE Transactions on Electron Devices. 67, 2, p. 711-716 6 p., 8951114.Research output: Contribution to journal › Article
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
Sung, P. J., Su, C. J., Lo, S. H., Hsueh, F. K., Lu, D. D., Lee, Y. J. & Chao, T. S., 1 Jan 2020, In : IEEE Journal of the Electron Devices Society. 8, p. 474-480 7 p., 9063644.Research output: Contribution to journal › Article
Open Access
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
Sung, P-J., Chang, S-W., Kao, K-H., Wu, C-T., Su, C-J., Cho, T-C., Hsueh, F-K., Lee, W-H., Lee, Y-J. & Chao, T-S., 23 Jul 2020, In : Ieee Transactions On Electron Devices. 67, 9, p. 3504-3509 6 p.Research output: Contribution to journal › Article
Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
Shen, C. H., Chen, W. Y., Lee, S. Y., Kuo, P. Y. & Chao, T. S., 1 Jan 2020, In : IEEE Transactions on Nanotechnology. 19, p. 322-327 6 p., 9044627.Research output: Contribution to journal › Article
Prizes
Excellent Dean Researching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2009
Prize: Honorary award
Excellent Research Awarded by College of Science, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2005
Prize: Honorary award
Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2007
Prize: Honorary award
Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2015
Prize: Honorary award
Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2004
Prize: Honorary award