Projects per year
Personal profile
Research Interests
Physics of Semiconductor Devices, Thin Films Deposition Techniques, ULSI Technology, Deep-Submicron Devices Fabrications, Ultra-thin Oxide Preparations, Ultra-clean Processes
Experience
1992/7-2001/8 Associate Researcher / Researcher, National Nano Device Labs
2001/8-2002/1 Associate Prof., Dept. Of Electrophysics, NCTU
2002/2-present Prof., Dept. Of Electrophysics, NCTU
2009-2011 Chairman, Department of Electrophysics, NCTU, Taiwan
Education/Academic qualification
PhD, National Chiao Tung University
External positions
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Projects
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NCTU Core Facility Service Platform for Basic Research
1/01/21 → 31/12/21
Project: Government Ministry › Ministry of Science and Technology
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利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
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利用堆疊型閘極全環繞技術結合鉿基鐵電材料開發應用於以人工神經網路為基礎之邊緣運算低功耗元件
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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Service Proposal for Precious Instruments of National Chiao-Tung University
1/12/19 → 31/03/21
Project: Government Ministry › Ministry of Science and Technology
Research output
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CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications
Kuo, Y. S., Lee, S. Y., Lee, C. C., Li, S. W. & Chao, T-S., Feb 2021, In: IEEE Transactions on Electron Devices. 68, 2, p. 879-884 6 p., 9316796.Research output: Contribution to journal › Article › peer-review
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Ultrathin Sub-5-nm Hf1-xZrxO2for a Stacked Gate-all-Around Nanowire Ferroelectric FET with Internal Metal Gate
Lee, S. Y., Lee, C. C., Kuo, Y. S., Li, S. W. & Chao, T. S., 2021, In: IEEE Journal of the Electron Devices Society. 9, p. 236-241 6 p., 9344700.Research output: Contribution to journal › Article › peer-review
Open Access -
Characteristics of Poly-Si Junctionless FinFETs with HfZrO Using Forming Gas Annealing
Chung, S. T., Lee, Y. J. & Chao, T. S., 1 Jan 2020, In: IEEE Transactions on Nanotechnology. 19, p. 390-396 7 p., 9091928.Research output: Contribution to journal › Article › peer-review
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Crystallinity Effect on Reliability of Sidewall Damascened Nanowire Poly-Si GAA FETs
Shen, C. H., Chen, W. Y., Chung, C. C., Huang, Y. E. & Chao, T-S., Jun 2020, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc., p. 53-54 2 p. 9131624. (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., Feb 2020, In: IEEE Transactions on Electron Devices. 67, 2, p. 711-716 6 p., 8951114.Research output: Contribution to journal › Article › peer-review
Prizes
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Excellent Dean Researching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2009
Prize: Honorary award
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Excellent Research Awarded by College of Science, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2005
Prize: Honorary award
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Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2004
Prize: Honorary award
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Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2007
Prize: Honorary award
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Meritorious Teaching Award, National Chiao Tung University
Chao, Tien-Sheng (Recipient), 2015
Prize: Honorary award