Projects per year
Personal profile
Research Interests
Reliability of Semiconductor Devices, Flash Memory, High-speed Devices and Circuits
Experience
Education/Academic qualification
PhD, University of Illinois at Urbana-Champaign
External positions
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Dive into the research topics where Ta-Hui Wang is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects
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Accelerating Qualification Method for Data Retention in Post-SET/RESET Cycling RRAM and its Theory and Statistical Models.
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Frequency Response and Reliability in Negative Capacitance FET
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Frequency Response and Reliability in Negative Capacitance FET
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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Accelerating Qualification Method for Data Retention in Post-SET/RESET Cycling RRAM and its Theory and Statistical Models.
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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3D V-NAND Reliability Characterization and SiN Charge Transport
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
Research Output
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Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
Su, P. C., Jiang, C. M., Chen, Y. J., Wang, C. C., Li, K. S., Lin, C. C. & Wang, T., Jan 2020, In: IEEE Transactions on Electron Devices. 67, 1, p. 113-117 5 p., 8935500.Research output: Contribution to journal › Article › peer-review
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Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
Chiang, H. L., Chen, T. C., Song, M. Y., Chen, Y. S., Chiu, J. P., Chiang, K., Manfrini, M., Cai, J., Gallagher, W. J., Wang, T., Diaz, C. H. & Wong, H. S. P., Aug 2020, In: IEEE Transactions on Electron Devices. 67, 8, p. 3102-3108 7 p., 9139332.Research output: Contribution to journal › Article › peer-review
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Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
Lu, C. C., Cheng, C. C., Chiu, H. P., Lin, W. L., Chen, T. W., Ku, S. H., Tsai, W. J., Lu, T. C., Chen, K. C., Wang, T-H. & Lu, C. Y., 16 Jan 2019, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 2.2.1-2.2.4 8614548. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on Vt Retention Loss in a Multilevel Charge Trap Flash Memory
Liu, Y. H., Zhan, T. C., Wang, T., Tsai, W. J., Lu, T. C., Chen, K. C. & Lu, C. Y., Dec 2019, In: IEEE Transactions on Electron Devices. 66, 12, p. 5155-5161 7 p., 8895844.Research output: Contribution to journal › Article › peer-review
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Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory
Lin, T. W., Ku, S. H., Cheng, C. H., Lee, C. W., Ijen-Huang, Tsai, W. J., Lu, T. C., Lu, W. P., Chen, K. C., Wang, T-H. & Lu, C. Y., 25 May 2018, 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., p. PMY.61-PMY.65 (IEEE International Reliability Physics Symposium Proceedings; vol. 2018-March).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review