Projects per year
Personal profile
Research Interests
Digital IC design, memory circuits and memory sub-system design, hardware design for AI and machine learning acceleration, 3D-IC design (Monolithic 3D-IC & TSV 3D-IC)
Experience
Education/Academic qualification
PhD, National Chiao Tung University
External positions
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Projects
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Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
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Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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Design of Ultra-High-Density Neural-Signal Acquisition Circuits with Optical Transmission
1/08/19 → 31/10/20
Project: Government Ministry › Ministry of Science and Technology
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Design of Ultra-High-Density Neural-Signal Acquisition Circuits with Optical Transmission
1/08/18 → 31/10/19
Project: Government Ministry › Ministry of Science and Technology
Research output
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Design and Implementation for Deep Learning-based Adjustable Beamforming Training for Millimeter Wave Communication Systems
Shen, L. H., Chang, T. W., Feng, K. T. & Huang, P. T., 2021, (Accepted/In press) In: IEEE Transactions on Vehicular Technology.Research output: Contribution to journal › Article › peer-review
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Rotational motion-aware beam refinement for high-throughput mmWave communications
Singh, T. H., Jigalur, S. B. & Huang, P. T., 2021, (Accepted/In press) In: Wireless Networks.Research output: Contribution to journal › Article › peer-review
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3D On-Demand Flying Mobile Communication for Millimeter Wave Heterogeneous Networks
Feng, K-T., Shen, L. H., Li, C. Y., Huang, P-T., Wu, S-H., Wang, L-C., Lin, Y-B. & Chang, M-C., Sep 2020, In: IEEE Network. 34, 5, p. 198-204 7 p.Research output: Contribution to journal › Article › peer-review
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Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs
Lo, C. Y., Huang, P. T. & Hwang, W., Aug 2020, Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020. Institute of Electrical and Electronics Engineers Inc., p. 320-323 4 p. 9073944. (Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Ultrahigh responsivity and tunable photogain BEOL compatible MoS}_{2} phototransistor array for monolithic 3D image sensor with block-level sensing circuits
Yang, C. C., Hsieh, P. Y., Chen, P. H., Hsieh, T. Y., Huang, P. T., Lin, Y. T., Shen, C. H., Shieh, J. M., Chang, D. C., Yeh, W. K., Wu, M. C. & Lee, Y. H., Jun 2020, 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9265017. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2020-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review