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Personal profile

Research Interests

Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices

Experience

Education/Academic qualification

PhD, University of California, Berkeley

External positions

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Projects

Investigation and Modeling for 2D-FeFET based Nonvolatile Memory

Su, P.

1/08/2031/07/21

Project: Government MinistryMinistry of Science and Technology

Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs

Su, P.

1/08/1931/07/20

Project: Government MinistryMinistry of Science and Technology

Investigation and Modeling for 2D-FeFET based Nonvolatile Memory

Su, P.

1/08/1931/07/20

Project: Government MinistryMinistry of Science and Technology

Modeling and Design Space Exploration for Negative-Capacitance FETs with 2D-Material Channel

Su, P.

1/08/1831/07/19

Project: Government MinistryMinistry of Science and Technology

Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs

Su, P.

1/08/1831/07/19

Project: Government MinistryMinistry of Science and Technology

Research Output

A New 8T Hybrid Nonvolatile SRAM with Ferroelectric FET

You, W. X., Su, P. & Hu, C., 7 Feb 2020, In : IEEE Journal of the Electron Devices Society. 8, 1, p. 171-175 5 p., 8986584.

Research output: Contribution to journalArticle

Open Access
  • 1 Scopus citations
    Open Access
  • Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

    Liu, Y. S. & Su, P., Mar 2020, In : IEEE Electron Device Letters. 41, 3, p. 369-372 4 p., 8962180.

    Research output: Contribution to journalArticle

  • 1 Scopus citations

    A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

    Tang, Y. T., Fang, C. L., Kao, Y. C., Modolo, N., Su, C. J., Wu, T. L., Kao, K. H., Wu, P. J., Hsaio, S. W., Useinov, A., Su, P., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., Jun 2019, 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. T222-T223 2 p. 8776508. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2019-June).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Analysis and Design of InGaAs Negative-Capacitance FinFETs considering Quantum Capacitance

    Huang, S. E., Lin, S. H. & Su, P., Mar 2019, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc., p. 20-22 3 p. 8731312. (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution