Pin Su

Professor

https://orcid.org/0000-0002-8213-4103

Phone03-5754142
Emailpinsu@mail.nctu.edu.tw
Websitehttp://www.ee.nctu.edu.tw/People/Professor/individual.php?index=24

Research activity per year

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Personal profile

Research Interests

Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices

Experience

Education/Academic qualification

PhD, University of California, Berkeley

External positions

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1 Active
15 Finished

Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
Su, P.
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs
Su, P.
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
Su, P.
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
Modeling and Design Space Exploration for Negative-Capacitance FETs with 2D-Material Channel
Su, P.
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs
Su, P.
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology

108 Conference contribution
98 Article
5 Patent
4 Paper
More

A New 8T Hybrid Nonvolatile SRAM with Ferroelectric FET
You, W. X., Su, P. & Hu, C., 7 Feb 2020, In: IEEE Journal of the Electron Devices Society. 8, 1, p. 171-175 5 p., 8986584.
Research output: Contribution to journal › Article › peer-review

Open Access
1 Scopus citations
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
Huang, S. E., Lin, S. H. & Su, P., 14 Jan 2020, In: IEEE Journal of the Electron Devices Society. 8, p. 105-109 5 p., 8959139.
Research output: Contribution to journal › Article › peer-review

Open Access
Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers
Lin, C. C., Wu, Y. J., You, W. X. & Su, P., Aug 2020, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., p. 62-63 2 p. 9203647. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation
Wu, F. C., You, W. X. & Su, P., Aug 2020, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., p. 78-79 2 p. 9203737. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
Liu, Y. S. & Su, P., Mar 2020, In: IEEE Electron Device Letters. 41, 3, p. 369-372 4 p., 8962180.
Research output: Contribution to journal › Article › peer-review
2 Scopus citations