Projects per year
Personal profile
Research Interests
AI computing platform design, approximate computing for AI applications, cybersecurity and hardware Trojan, SoC design automation
Experience
1.Software Engineer, Design Technology Solutions, Intel Corporation, 08/2011 – 07/2013
2.Research Assistant, Energy Aware Computing (EnyAC) Group, Carnegie Mellon University, 08/2006 – 07/2011
Education/Academic qualification
PhD, Carnegie Mellon University
External positions
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Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects
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Edge-deployment-aware Vision DNN Architecture and Module Design
1/05/20 → 30/04/21
Project: Government Ministry › Ministry of Science and Technology
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Edge-deployment-aware Vision DNN Architecture and Module Design
1/05/19 → 30/04/20
Project: Government Ministry › Ministry of Science and Technology
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教育部智慧聯網技術與應用人才培育計畫-108年度智慧聯網技術與應用跨校教學聯盟中心-課程(模組)發展計畫-工業物聯網安全及連網整合技術
1/04/19 → 31/03/20
Project: Government Ministry › Ministry of Education(Include School)
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智慧終端系統晶片研發與新創事業計畫－子計畫二：以終端系統為考量之視覺深度神經網路模組設計(1/2)
1/05/18 → 30/04/19
Project: Government Ministry › Ministry of Science and Technology
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教育部智慧聯網技術與應用人才培育計畫 -- 智慧製造電子應用聯盟-課程(模組)發展計畫-工業物聯網安全及連網整合技術--電子產品製造供應鏈之硬體防護設計及自動化
6/11/17 → 31/03/19
Project: Government Ministry › Ministry of Education(Include School)
Research Output
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CNN-based Stochastic Regression for IDDQ Outlier Identification
Chen, C. T., Yen, C. H., Wen, C. Y., Yang, C. H., Wu, K. C., Chern, M., Chen, Y. Y., Kuo, C. Y., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Apr 2020, Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 9107570. (Proceedings of the IEEE VLSI Test Symposium; vol. 2020-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator
Liu, S. M., Tang, L., Huang, N. C., Tsai, D. Y., Yang, M. X. & Wu, K. C., Aug 2020, 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc., 9196335. (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Selective sensor placement for cost-effective online aging monitoring and resilience
Chang, H. C., Huang, L. A., Wu, K. C. & Chen, Y. G., 20 Sep 2020, ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, p. 95-102 8 p. (Proceedings of the International Symposium on Physical Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access -
Aging-aware chip health prediction adopting an innovative monitoring strategy
Wang, Y. T., Wu, K-C., Chou, C. H. & Chang, S. C., 21 Jan 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 179-184 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
Huang, N. C., Chen, Y. G. & Wu, K. C., Jul 2019, Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, p. 218-223 6 p. 8839460. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2019-July).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Prizes
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Distinguished Mentor Award, National Chiao Tung University
Wu, Kai-Chiang (Recipient), 2016
Prize: Honorary award
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Distinguished Mentor Award, National Chiao Tung University
Wu, Kai-Chiang (Recipient), 2015
Prize: Honorary award
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