Projects per year
Personal profile
Research Interests
Electronic Design Automation, Design and Analysis of Algorithms, Combinatorial Optimization
Experience
Education/Academic qualification
PhD, University of Texas at Austin
External positions
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Projects
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以記憶體為中心的人工智慧邊緣產品EDA方案: 具重新配置能力的系統評估與實作(2/3)
1/11/20 → 31/10/21
Project: Government Ministry › Ministry of Science and Technology
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Machine and Deep Learning Based Circuit and Layout Synthesis for
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Machine and Deep Learning Based Circuit and Layout Synthesis for
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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EDA Solutions For Memory-Centric AI Edge: System Evaluation and Implementation for Reconfigurability
1/11/19 → 31/12/20
Project: Government Ministry › Ministry of Science and Technology
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Machine and Deep Learning Based Circuit and Layout Synthesis for Digital and Analog Designs
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
Research Output
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Achieving Analog Layout Integrity through Learning and Migration Invited Talk
Lin, M. P. H., Chi, H. Y., Patyal, A., Liu, Z. Y., Zhao, J. J., Liu, C-N. & Chen, H-M., 2 Nov 2020, In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2020-November, 9256451.Research output: Contribution to journal › Conference article › peer-review
Open Access -
A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design
Huang, M. Y., Chen, H-M., Chen, K. N., Wu, S. H., Lee, Y. M. & Su, A. Y., Jun 2020, Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020. Institute of Electrical and Electronics Engineers Inc., p. 2236-2241 6 p. 9159244. (Proceedings - Electronic Components and Technology Conference; vol. 2020-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Exploring Multiple Analog Placements with Partial-Monotonic Current Paths and Symmetry Constraints using PCP-SP
Patyal, A., Pan, P. C., A, A. K., Chen, H. M. & Chen, W. Z., 1 Jan 2020, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review
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Irregular Bumps Design Planning for Modern Ball Grid Array Packages
Chang, H. Y., Chen, H. M., Kuo, Y. C., Tsai, H. T., Chen, S. Y. H., Jiang, J. R., Chien, Y. Y. & Chen, Y. Y., Jun 2020, Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020. Institute of Electrical and Electronics Engineers Inc., p. 1838-1843 6 p. 9159462. (Proceedings - Electronic Components and Technology Conference; vol. 2020-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Late breaking results: Pole-aware analog placement considering monotonic current flow and crossing-wire minimization
Patyal, A., Chen, H-M. & Lin, M. P. H., Jul 2020, 2020 57th ACM/IEEE Design Automation Conference, DAC 2020. Institute of Electrical and Electronics Engineers Inc., 9218634. (Proceedings - Design Automation Conference; vol. 2020-July).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review