1993 …2021

Research output per year

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Personal profile

Research Interests

VLSI Circuits & Systems, Circuit Design, Semiconductor Devices

Experience

Education/Academic qualification

PhD, National Chiao Tung University

External positions

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Projects

A novel T-gate RF technology platform for IoT and high-end RF

Lin, H.

1/08/2031/07/21

Project: Government MinistryMinistry of Science and Technology

Development Of Advanced Power And IoT RF Device Technologies

Lin, H.

1/01/2031/12/20

Project: Government MinistryMinistry of Science and Technology

智慧終端半導體製程與晶片系統研發專案計畫(半導體射月計畫)推動辦公室

Lin, H.

1/01/2031/12/20

Project: Government MinistryMinistry of Science and Technology

A novel T-gate RF technology platform for IoT and high-end RF

Lin, H.

1/08/2131/07/22

Project: Government MinistryMinistry of Science and Technology

智慧終端半導體製程與晶片系統研發專案計畫(半導體射月計畫)推動辦公室

Lin, H.

1/01/2131/12/21

Project: Government MinistryMinistry of Science and Technology

Research Output

A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors

Huang, Y. A., Peng, K. P., Meng, Y. C., Su, C. J., Li, P. W. & Lin, H. C., 1 Apr 2020, In : Japanese Journal of Applied Physics. 59, SG, 6 p., SGGJ01.

Research output: Contribution to journalArticle

Open Access
  • A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si with High Etching Selectivity and Isotropy

    Huang, Y. A., Liang, C. Y., Peng, K. P., Chen, K. M., Huang, G. W., Li, P-W. & Lin, H-C., Mar 2020, In : IEEE Electron Device Letters. 41, 3, p. 397-400 4 p., 8977479.

    Research output: Contribution to journalArticle

  • Coordinated and Simultaneous Formation of Paired Ge Quantum Dots by Thermal Oxidation of Designer Poly-SiGe Spacer Structures

    Chen, H. Y., Peng, K. P., George, T., Lin, H. C. & Li, P. W., 2020, In : IEEE Transactions on Nanotechnology. 19, p. 436-438 3 p., 9088228.

    Research output: Contribution to journalArticle

  • Impact of asymmetrical source/drain offsets on the operation of dual-gated poly-Si junctionless nanowire transistors

    Chang, Y. T., Wu, R. J., Peng, K. P., Su, C. J., Li, P. W. & Lin, H. C., Nov 2020, In : Vacuum. 181, 109613.

    Research output: Contribution to journalArticle

  • Improving breakdown voltage for 120 v level up shifter by using vertical and lateral assisted depletion layers in 0.35 μm CMOS technology

    Ningaraju, V., Lin, H. C., Chen, P. A. & Lin, K. L., 1 Apr 2020, In : Japanese Journal of Applied Physics. 59, SG, SGGD15.

    Research output: Contribution to journalArticle