19992021

Research output per year

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Personal profile

Research Interests

EDA, Analog Behavioral Modeling, High-level Power Modeling, Verification of System-level Integration

Experience

Education/Academic qualification

PhD, National Chiao Tung University

External positions

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Projects

AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems (II)

Liu, C.

1/08/2031/07/21

Project: Government MinistryMinistry of Science and Technology

AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems (II)

Liu, C.

1/08/2131/07/22

Project: Government MinistryMinistry of Science and Technology

AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems

Liu, C.

1/08/1931/07/20

Project: Government MinistryMinistry of Science and Technology

Sample Preparation for Flow-Based Microfluidic Biochips

Liu, C.

1/08/1831/07/19

Project: Government MinistryMinistry of Science and Technology

Sample Preparation for Flow-Based Microfluidic Biochips

Liu, C.

1/08/1731/07/18

Project: Government MinistryMinistry of Science and Technology

Research Output

Achieving routing integrity in analog layout migration via cartesian detection lines

Chi, H. Y., Lin, Z. J., Hung, C. H., Liu, C. N. J. & Chen, H. M., Nov 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 8942088. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Structure-Based Methodology for Analog Layout Generation

    Chen, Y. H., Chi, H. Y., Song, L. Y., Liu, C. N. J. & Chen, H. M., Jul 2019, SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 33-36 4 p. 8795227. (SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Modelling and optimisation algorithm for length-matching escape routing of differential pairs

    Li, T. H., Chen, J. E., Chen, T. C. & Liu, C-N., 1 Jan 2019, In : Electronics Letters. 55, 10, p. 603-605 3 p.

    Research output: Contribution to journalArticle

  • Analog placement with current flow and symmetry constraints using PCP-SP

    Patyal, A., Pan, P. C., Asha, K. A., Chen, H-M., Chi, H. Y. & Liu, C-N., 24 Jun 2018, Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., a10. (Proceedings - Design Automation Conference; vol. Part F137710).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2 Scopus citations

    An incremental aging analysis method based on delta circuit simulation technique

    He, S. R., Qui, N. C., Kuo, Y. H. & Liu, C-N., 24 Jan 2018, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. IEEE Computer Society, p. 60-65 6 p. (Proceedings of the Asian Test Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution