Projects per year
Personal profile
Research Interests
VLSI Testing, Statistical Timing Analysis, Physical Design Automation, Test Compression/Compaction
Experience
Education/Academic qualification
PhD, University of California, Santa Barbara
External positions
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Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects
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Power-Distribution-Network Generation for Optimizing IR-Drop Aware Timing
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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EDA Tool and Machine Learning Platform for IDDQ Testing
1/01/20 → 31/12/20
Project: Government Ministry › Ministry of Science and Technology
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Power-Distribution-Network Generation for Optimizing IR-Drop Aware Timing
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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Faster-than-1-measuremnt-per-DUT WAT test structure for measuring Vt
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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EDA Tool and Machine Learning Platform for IDDQ Testing
1/01/19 → 31/12/19
Project: Government Ministry › Ministry of Science and Technology
Research Output
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CNN-based Stochastic Regression for IDDQ Outlier Identification
Chen, C. T., Yen, C. H., Wen, C. Y., Yang, C. H., Wu, K. C., Chern, M., Chen, Y. Y., Kuo, C. Y., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Apr 2020, Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 9107570. (Proceedings of the IEEE VLSI Test Symposium; vol. 2020-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
Chang, W. H., Lin, L. Y., Chen, Y. G. & Chao, M. C. T., 2 Nov 2020, In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2020-November, 9256540.Research output: Contribution to journal › Conference article › peer-review
Open Access -
Transforming global routing report into DRC violation map with convolutional neural network
Hung, W. T., Huang, J. Y., Chou, Y. C., Tsai, C. H. & Chao, M., 20 Sep 2020, ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, p. 57-64 8 p. (Proceedings of the International Symposium on Physical Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access -
Layout-Based Dual-Cell-Aware Tests
Wu, T. W., Lee, D. Z., Wu, K-C., Huang, Y. H., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, C-T., 1 Apr 2019, 2019 IEEE 37th VLSI Test Symposium, VTS 2019. IEEE Computer Society, 8758646. (Proceedings of the IEEE VLSI Test Symposium; vol. 2019-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Methodology of generating timing-slack-based cell-aware tests
Nien, Y. T., Wu, K. C., Lee, D. Z., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Nov 2019, 2019 IEEE International Test Conference, ITC 2019. Institute of Electrical and Electronics Engineers Inc., 9000119. (Proceedings - International Test Conference; vol. 2019-November).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review