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Chia-Tso Chao

Professor

19992020

Research output per year

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Personal profile

Research Interests

VLSI Testing, Statistical Timing Analysis, Physical Design Automation, Test Compression/Compaction

Experience

Education/Academic qualification

PhD, University of California, Santa Barbara

External positions

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Projects

Power-Distribution-Network Generation for Optimizing IR-Drop Aware Timing

Chao, C.

1/08/20 → 31/07/21

Project: Government Ministry › Ministry of Science and Technology

EDA Tool and Machine Learning Platform for IDDQ Testing

Chao, C.

1/01/20 → 31/12/20

Project: Government Ministry › Ministry of Science and Technology

Faster-than-1-measuremnt-per-DUT WAT test structure for measuring Vt

Chao, C.

1/08/19 → 31/07/20

Project: Government Ministry › Ministry of Science and Technology

Power-Distribution-Network Generation for Optimizing IR-Drop Aware Timing

Chao, C.

1/08/19 → 31/07/20

Project: Government Ministry › Ministry of Science and Technology

EDA Tool and Machine Learning Platform for IDDQ Testing

Chao, C.

1/01/19 → 31/12/19

Project: Government Ministry › Ministry of Science and Technology

Research Output

  • 44 Conference contribution
  • 18 Article
  • 3 Conference article

CNN-based Stochastic Regression for IDDQ Outlier Identification

Chen, C. T., Yen, C. H., Wen, C. Y., Yang, C. H., Wu, K. C., Chern, M., Chen, Y. Y., Kuo, C. Y., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Apr 2020, Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 9107570. (Proceedings of the IEEE VLSI Test Symposium; vol. 2020-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    • Transforming global routing report into DRC violation map with convolutional neural network

    Hung, W. T., Huang, J. Y., Chou, Y. C., Tsai, C. H. & Chao, M., 20 Sep 2020, ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, p. 57-64 8 p. (Proceedings of the International Symposium on Physical Design).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Open Access

    • Layout-Based Dual-Cell-Aware Tests

    Wu, T. W., Lee, D. Z., Wu, K-C., Huang, Y. H., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, C-T., 1 Apr 2019, 2019 IEEE 37th VLSI Test Symposium, VTS 2019. IEEE Computer Society, 8758646. (Proceedings of the IEEE VLSI Test Symposium; vol. 2019-April).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    • Methodology of generating timing-slack-based cell-aware tests

    Nien, Y. T., Wu, K. C., Lee, D. Z., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Nov 2019, 2019 IEEE International Test Conference, ITC 2019. Institute of Electrical and Electronics Engineers Inc., 9000119. (Proceedings - International Test Conference; vol. 2019-November).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    • Micro-architecture optimization for low-power bitcoin mining ASICs

    Wang, Y. Z., Wu, J., Chen, S. H., Chao, M. C. T. & Yang, C. H., Apr 2019, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741726. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution