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Personal profile

Research Interests

Sensor Interface Circuits, Data Converters, Phase-locked Loop and Frequency Synthesizer, High-speed Wireline Transceivers and Building Blocks, DC-DC Power Converters

Experience

2013/12~2014/11 Senior Analog Design Engineer, Mediatek USA

2015/8~2016/12 Staff Analog Design Engineer, Faraday Technology USA

2017/1~2018/8 Technical Manager, Egis Technology Inc.

2018/8~Assistant Professor, Electrical and Computer Engineering, National Chiao Tung University

Education/Academic qualification

PhD, Oregon State University

External positions

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Projects

High-Precision Micro-Power Analog-to-Digital Converters for IoT Sensor Interfaces

Chen, C.

1/01/2031/12/20

Project: Government MinistryMinistry of Science and Technology

High-Precision Micro-Power Analog-to-Digital Converters for IoT Sensor Interfaces

Chen, C.

1/01/2131/12/21

Project: Government MinistryMinistry of Science and Technology

High-Precision Micro-Power Analog-to-Digital Converters for IoT Sensor Interfaces

Chen, C.

1/01/1931/12/19

Project: Government MinistryMinistry of Science and Technology

Research Output

Robust continuous-time mash delta sigma modulator

Wang, Y., Shi, L., He, T., Zhang, Y., Chen, C-H. & Temes, G. C., 22 Jan 2019, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 310-313 4 p. 8624017. (Midwest Symposium on Circuits and Systems; vol. 2018-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations

    A 16 b Multi-Step Incremental Analog-To-Digital Converter with Single-Opamp Multi-Slope Extended Counting

    Zhang, Y., Chen, C-H., He, T. & Temes, G. C., 1 Apr 2017, In : IEEE Journal of Solid-State Circuits. 52, 4, p. 1066-1076 11 p., 7833069.

    Research output: Contribution to journalArticle

    Open Access
  • 17 Scopus citations

    A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW

    Zhang, Y., Chen, C-H., He, T., Sobue, K., Hamashita, K. & Temes, G. C., 26 Jul 2017, 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 7993660. (Proceedings of the Custom Integrated Circuits Conference; vol. 2017-April).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 4 Scopus citations

    Incremental ADC with parallel counting

    He, T., Chen, C-H., Zhang, Y. & Temes, G. C., 27 Sep 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., p. 1017-1020 4 p. 8053099. (Midwest Symposium on Circuits and Systems; vol. 2017-August).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A 35μW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator

    Zhang, Y., Chen, C-H., He, T. & Temes, G. C., 21 Sep 2016, 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc., 7573464. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2016-September).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 6 Scopus citations