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Personal profile

Research Interests

High-k Dielectric for Nanoscale Devices, Organic Thin-film-transistor & Memory, Nanocrystal Nonvolatile Memory, Post-Si High-mobility Channel MOSFET

Experience

Education/Academic qualification

PhD, National Chiao Tung University

External positions

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Projects

Process development of novel two-dimensional material: HfS2 andHfSe2 doping technology and device fabrication

Chien, C.

1/08/2031/07/21

Project: Government MinistryMinistry of Science and Technology

產學合作計畫-碳化矽溝槽式金氧半場效應電晶體技術開發(3/3)

Chien, C.

1/11/1931/10/20

Project: Government MinistryMinistry of Science and Technology

Research Output

Impact of the Crystal Phase of ZrO on Charge Trapping Memtransistor as Synaptic Device for Neural Network Application

Chou, Y. C., Tsai, C. W., Yi, C. Y., Chung, W. H. & Chien, C. H., 2020, In : IEEE Journal of the Electron Devices Society. 8, p. 572-576 5 p., 9091548.

Research output: Contribution to journalArticle

Open Access
  • Study of E-Mode AlGaN/GaN MIS-HEMT with La-silicate Gate Insulator for Power Applications

    Huang, K. N., Lin, Y. C., Lin, J. C., Hsu, C. C., Lee, J. H., Wu, C. H., Yao, J. N., Hsu, H-T., Nagarajan, V., Kakushima, K., Tsutsui, K., Iwai, H., Chien, C-H. & Chang, E. Y., Feb 2020, In : Journal of Electronic Materials. 49, 2, p. 1348-1353 6 p.

    Research output: Contribution to journalArticle

  • Comparison of Experimentally Extracted Top and Edge Contact Resistivity by TLM Structure with Two-step Sulfurization Nb-Doped MoS2

    Li, C. F., Chung, Y. Y., Lin, C. T., Ho, Y. T. & Chien, C. H., Mar 2019, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc., p. 191-193 3 p. 8731069. (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology

    Chung, Y. Y., Shieh, J. M., Su, S. K., Chiang, H. L., Chen, T. C., Li, L. J., Wong, H. S. P., Jian, W. B., Chien, C. H., Lu, K. C., Cheng, C. C., Li, M. Y., Lin, C. T., Li, C. F., Chen, J. H., Lai, T. Y. & Li, K. S., Dec 2019, In : IEEE Transactions on Electron Devices. 66, 12, p. 5381-5386 6 p., 8889483.

    Research output: Contribution to journalArticle

  • Demonstration of HfO 2 -Based Gate Dielectric with Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti into Interfacial Layer

    Tsai, Y. H., Chou, C. H., Chung, Y. Y., Yeh, W. K., Lin, Y. H., Ko, F-H. & Chien, C-H., 1 Feb 2019, In : IEEE Electron Device Letters. 40, 2, p. 174-176 3 p., 8579236.

    Research output: Contribution to journalArticle